Cypress CY7C1380D, CY7C1380F, CY7C1382F manual Features, Functional Description, Selection Guide

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

■Supports bus operation up to 250 MHz

■Available speed grades are 250, 200, and 167 MHz

■Registered inputs and outputs for pipelined operation

■3.3V core power supply

■2.5V or 3.3V I/O power supply

■Fast clock-to-output times

❐ 2.6 ns (for 250 MHz device)

■Provides high performance 3-1-1-1 access rate

■User selectable burst counter supporting Intel Pentium® inter- leaved or linear burst sequences

■Separate processor and controller address strobes

■Synchronous self-timed write

■Asynchronous output enable

■Single cycle chip deselect

■CY7C1380D/CY7C1382D is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package; CY7C1380F/CY7C1382F is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA and 165-ball FBGA package

■IEEE 1149.1 JTAG-Compatible Boundary Scan

■ZZ sleep mode option

Functional Description

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F[1] SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3 [2]), burst control

inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin (ADV).

Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations (see Table 1 on page 6 and “Truth Table” on page 10 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F operates from a +3.3V core power supply while all outputs operate with a +2.5 or +3.3V power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

Description	250 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	2.6	3.0	3.4	ns
Maximum Operating Current	350	300	275	mA
Maximum CMOS Standby Current	70	70	70	mA

Notes

1.For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2.CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

Cypress Semiconductor Corporation • 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05543 Rev. *F		Revised January 12, 2009

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