Cypress CY7C1382D, CY7C1380F Maximum Ratings, Electrical Characteristics Over the Operating Range

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested.

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND		–0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State	–0.5V to VDDQ + 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage	–0.5V to VDD + 0.5V
Current into Outputs (LOW)	20 mA
Static Discharge Voltage	>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current	>200 mA

Operating Range

	Range	Ambient	VDD	VDDQ
		Temperature
	Commercial	0°C to +70°C	3.3V –5%/+10%	2.5V – 5%
				to VDD
	Industrial	–40°C to +85°C
[17, 18]

Parameter		Description	Test Conditions		Min	Max	Unit
VDD		Power Supply Voltage			3.135	3.6	V
VDDQ		I/O Supply Voltage	for 3.3V I/O		3.135	VDD	V
			for 2.5V I/O		2.375	2.625	V
VOH		Output HIGH Voltage	for 3.3V I/O, IOH = –4.0 mA		2.4		V
			for 2.5V I/O, IOH = –1.0 mA		2.0		V
VOL		Output LOW Voltage	for 3.3V I/O, IOL = 8.0 mA			0.4	V
			for 2.5V I/O, IOL = 1.0 mA			0.4	V
V	IH	Input HIGH Voltage [17]	for 3.3V I/O		2.0	V + 0.3V	V
						DD
			for 2.5V I/O		1.7	VDD + 0.3V	V
VIL		Input LOW Voltage [17]	for 3.3V I/O		–0.3	0.8	V
			for 2.5V I/O		–0.3	0.7	V
IX		Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	μA
		except ZZ and MODE
		Input Current of MODE	Input = VSS		–30		μA
			Input = VDD			5	μA
		Input Current of ZZ	Input = VSS		–5		μA
			Input = VDD			30	μA
IOZ		Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	μA
IDD		VDD Operating Supply	VDD = Max., IOUT = 0 mA,	4.0-ns cycle, 250 MHz		350	mA
		Current	f = fMAX = 1/tCYC	5.0-ns cycle, 200 MHz		300	mA
				6.0-ns cycle, 167 MHz		275	mA
ISB1		Automatic CE	VDD = Max, Device Deselected,	4.0-ns cycle, 250 MHz		160	mA
		Power Down	VIN ≥ VIH or VIN ≤ VIL	5.0-ns cycle, 200 MHz		150	mA
		Current—TTL Inputs	f = fMAX = 1/tCYC
				6.0-ns cycle, 167 MHz		140	mA
ISB2		Automatic CE Power	VDD = Max, Device Deselected,	All speeds		70	mA
		Down Current-CMOS	VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
		Inputs
ISB3		Automatic CE	VDD = Max, Device Deselected, or	4.0-ns cycle, 250 MHz		135	mA
		Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V	5.0-ns cycle, 200 MHz		130	mA
		Current—CMOS Inputs	f = fMAX = 1/tCYC
				6.0-ns cycle, 167 MHz		125	mA
ISB4		Automatic CE	VDD = Max, Device Deselected,	All speeds		80	mA
		Power Down	VIN ≥ VIH or VIN ≤ VIL, f = 0
		Current—TTL Inputs

Notes

17.Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).

18.TPower up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05543 Rev. *F Page 19 of 34

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