Cypress CY7C1382F Pin Definitions Name Description, Power supply inputs to the core of the device

										CY7C1380D, CY7C1382D
											CY7C1380F, CY7C1382F
Table 1. Pin Definitions
				Name			I/O		Description
	A0, A1, A						Input-	Address inputs used to select one of the address locations. Sampled at the rising edge of
							Synchronous	the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0
								are fed to the two-bit counter..
			A,			B	Input-	Byte write select inputs, active LOW. Qualified with			to conduct byte writes to the SRAM.
	BW				BW					BWE
	BWC, BWD						Synchronous	Sampled on the rising edge of CLK.
							Input-	Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
	GW
							Synchronous	global write is conducted (all bytes are written, regardless of the values on BWX and BWE).
							Input-	Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
	BWE
							Synchronous	asserted LOW to conduct a byte write.
	CLK						Input-	Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
							Clock	burst counter when ADV is asserted LOW, during a burst operation.
		1					Input-	Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
	CE
							Synchronous	CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled
								only when a new external address is loaded.
	CE2 [2]						Input-	Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
							Synchronous	with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
								address is loaded.
		3 [2]					Input-	Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
	CE
							Synchronous	CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address
								is loaded.
							Input-	Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
	OE
							Asynchronous	LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
								as input data pins. OE is masked during the first clock of a read cycle when emerging from a
								deselected state.
							Input-	Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
	ADV
							Synchronous	automatically increments the address in a burst cycle.
							Input-	Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
	ADSP
							Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
								are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
								recognized. ASDP is ignored when CE1 is deasserted HIGH.
							Input-	Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
	ADSC
							Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
								are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
								recognized.
	ZZ						Input-	ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
							Asynchronous	with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
								pin has an internal pull down.
	DQs, DQPX						I/O-	Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
							Synchronous	by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
								specified by the addresses presented during the previous clock rise of the read cycle. The
								direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
								When HIGH, DQs and DQPX are placed in a tri-state condition.
	VDD						Power Supply	Power supply inputs to the core of the device.
	VSS						Ground	Ground for the core of the device.
	VSSQ						I/O Ground	Ground for the I/O circuitry.
	VDDQ						I/O Power	Power supply for the I/O circuitry.
							Supply
Document #: 38-05543 Rev. *F											Page 6 of 34

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