Cypress CY7C1380D, CY7C1380F, CY7C1382F, CY7C1382D manual Burst Sequences, Sleep Mode, Address

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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Burst Sequences

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F provides a two-bit wraparound counter, fed by A1: A0, that imple- ments an interleaved or a linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.

Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Table 4. ZZ Mode Electrical Characteristics

Table 2. Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

01

00

11

10

10

11

00

01

11

10

01

00

Table 3. Linear Burst Address Table (MODE = GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Parameter

Description

Test Conditions

Min

Max

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD – 0.2V

 

80

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2V

 

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

 

ns

tZZI

ZZ Active to sleep current

This parameter is sampled

 

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

 

ns

Document #: 38-05543 Rev. *F

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Contents Functional Description FeaturesSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name Description Ground for the core of the devicePin Definitions TMSTCK Jtag Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional OverviewBurst Sequences Sleep ModeAddress A1 A0 Parameter Description Test Conditions MinOperation Add. Used Truth TableTruth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetReserved TAP TimingParameter Description Min Clock3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Range AmbientThermal Resistance CapacitancePackage EIA/JESD515V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 20 Setup TimesOutput Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistorySales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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