Cypress CY7C1380D, CY7C1380F manual Document History, Submission Orig. Description of Change Date

Page 33

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Document History Page

Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Document Number: 38-05543

REV.

ECN NO.

Submission

Orig. of

Description of Change

 

 

Date

Change

 

**

254515

See ECN

RKF

New data sheet

 

 

 

 

 

*A

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

 

 

 

 

non-compliance with 1149.1

 

 

 

 

Removed 225MHz and 133 MHz Speed Bins

 

 

 

 

Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages

 

 

 

 

Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

 

 

 

 

mation

*B

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as per

 

 

 

 

JEDEC standard

 

 

 

 

Added description on EXTEST Output Bus Tri-State

 

 

 

 

Changed description on the Tap Instruction Set Overview and Extest

 

 

 

 

Changed Device Width (23:18) for 119-BGA from 000000 to 101000

 

 

 

 

Added separate row for 165 -FBGA Device Width (23:18)

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08

 

 

 

 

°C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W

 

 

 

 

respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

 

 

 

 

mation

 

 

 

 

Updated Ordering Information Table

*C

416321

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

 

 

 

 

North First Street” to “198 Champion Court”

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage Current on

 

 

 

 

page# 18

 

 

 

 

Changed the IX current values of MODE on page # 18 from –5 μA and 30 μA

 

 

 

 

to –30 μA and 5 μA

 

 

 

 

Changed the IX current values of ZZ on page # 18 from –30 μA and 5 μA

 

 

 

 

to –5 μA and 30 μA

 

 

 

 

Changed VIH < VDD to VIH < VDDon page # 18

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated Ordering Information Table

*D

475009

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

 

 

 

 

Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

*E

776456

See ECN

VKN

Added Part numbers CY7C1380F and CY7C1382F and its related information

 

 

 

 

Added footnote# 3 regarding Chip Enable

 

 

 

 

Updated Ordering Information table

*F

2648065

01/27/09

VKN/PYRS

Modified note on top of the Ordering information table

 

 

 

 

Updated Ordering Information table to include CY7C1380F/CY7C1382F in 100-Pin

 

 

 

 

TSOP and 165 BGA package

Document #: 38-05543 Rev. *F

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Contents Functional Description FeaturesSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name Description Ground for the core of the devicePin Definitions TMSTCK Jtag Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional OverviewBurst Sequences Sleep ModeAddress A1 A0 Parameter Description Test Conditions MinOperation Add. Used Truth TableTruth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetReserved TAP TimingParameter Description Min Clock3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Range AmbientThermal Resistance CapacitancePackage EIA/JESD515V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 20 Setup TimesOutput Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistorySales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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