Cypress CY7C1380D, CY7C1380F manual AC Test Loads and Waveforms 3V I/O Test Load, 5V I/O Test Load

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CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F

Figure 9. AC Test Loads and Waveforms

3.3V I/O Test Load

3.3V

R = 317Ω

OUTPUT

VDDQ

ALL INPUT PULSES

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R = 351Ω

GND

≤ 1 ns

VT = 1.5V

INCLUDING

(c)

(a)

JIG AND

(b)

SCOPE

2.5V I/O Test Load

2.5V

R = 1667Ω

OUTPUT

ALL INPUT PULSES

VDDQ

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R = 1538Ω

GND

≤ 1 ns

VT = 1.25V

INCLUDING

(a)

JIG AND

(c)

SCOPE

(b)

90%

10%

≤ 1 ns

90%

10%

≤ 1 ns

Note

19. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05543 Rev. *F

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Contents Functional Description FeaturesSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name Description Ground for the core of the devicePin Definitions TMSTCK Jtag Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional OverviewBurst Sequences Sleep ModeAddress A1 A0 Parameter Description Test Conditions MinOperation Add. Used Truth TableTruth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetReserved TAP TimingParameter Description Min Clock3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Range AmbientThermal Resistance CapacitancePackage EIA/JESD515V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range 20 Setup TimesOutput Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistorySales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB