Cypress CY7C1382F, CY7C1380F, CY7C1380D, CY7C1382D manual A10 B10 P10

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

165-Ball BGA Boundary Scan Order [14, 16]

Bit #	Ball ID	Bit #	Ball ID	Bit #	Ball ID
1	N6	31	D10	61	G1

2	N7	32	C11	62	D2

3	N10	33	A11	63	E2

4	P11	34	B11	64	F2

5	P8	35	A10	65	G2

6	R8	36	B10	66	H1

7	R9	37	A9	67	H3

8	P9	38	B9	68	J1

9	P10	39	C10	69	K1

10	R10	40	A8	70	L1

11	R11	41	B8	71	M1

12	H11	42	A7	72	J2

13	N11	43	B7	73	K2

14	M11	44	B6	74	L2

15	L11	45	A6	75	M2

16	K11	46	B5	76	N1

17	J11	47	A5	77	N2

18	M10	48	A4	78	P1

19	L10	49	B4	79	R1

20	K10	50	B3	80	R2

21	J10	51	A3	81	P3

22	H9	52	A2	82	R3

23	H10	53	B2	83	P2

24	G11	54	C2	84	R4

25	F11	55	B1	85	P4

26	E11	56	A1	86	N5

27	D11	57	C1	87	P6

28	G10	58	D1	88	R6

29	F10	59	E1	89	Internal

30	E10	60	F1

Note

16. Bit# 89 is pre-set HIGH.

Document #: 38-05543 Rev. *F

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Contents Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Pin Definitions Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the devicePin Definitions TMSTCK Jtag Single Write Accesses Initiated by Adsc Single Write Accesses Initiated by AdspSingle Read Accesses Functional OverviewAddress Sleep ModeBurst Sequences A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedTruth Table for Read/Write 4 Function CY7C1380D/CY7C1380FFunction CY7C1382D/CY7C1382F TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Description Min TAP TimingReserved Clock5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Range AmbientPackage CapacitanceThermal Resistance EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadSwitching Characteristics Over the Operating Range 20 Setup TimesOutput Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB