Cypress CY7C1380D, CY7C1380F, CY7C1382F, CY7C1382D manual 167

Page 29

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

	Speed		Package	Part and Package Type	Operating
	(MHz)	Ordering Code	Diagram	Part and Package Type	Range
	(MHz)	Ordering Code	Diagram		Range
	167	CY7C1380D-167AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Commercial

		CY7C1382D-167AXC

		CY7C1380F-167AXC

		CY7C1382F-167AXC

		CY7C1380F-167BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

		CY7C1382F-167BGC

		CY7C1380F-167BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

		CY7C1382F-167BGXC

		CY7C1380D-167BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

		CY7C1382D-167BZC

		CY7C1380F-167BZC

		CY7C1382F-167BZC

		CY7C1380D-167BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

		CY7C1382D-167BZXC

		CY7C1380F-167BZXC

		CY7C1382F-167BZXC

		CY7C1380D-167AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Industrial

		CY7C1382D-167AXI

		CY7C1380F-167AXI

		CY7C1382F-167AXI

		CY7C1380F-167BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

		CY7C1382F-167BGI

		CY7C1380F-167BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

		CY7C1382F-167BGXI

		CY7C1380D-167BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

		CY7C1382D-167BZI

		CY7C1380F-167BZI

		CY7C1382F-167BZI

		CY7C1380D-167BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

		CY7C1382D-167BZXI

		CY7C1380F-167BZXI

		CY7C1382F-167BZXI

Document #: 38-05543 Rev. *F

Page 29 of 34

[+] Feedback

Image 29

Contents Functional Description FeaturesSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name Description Ground for the core of the deviceTCK Jtag Pin DefinitionsTMS Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional OverviewBurst Sequences Sleep ModeAddress A1 A0 Parameter Description Test Conditions MinOperation Add. Used Truth TableFunction CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetReserved TAP TimingParameter Description Min Clock3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Range AmbientThermal Resistance CapacitancePackage EIA/JESD515V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadOutput Times Switching Characteristics Over the Operating Range 20Setup Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistoryUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions