Cypress CY7C1382D, CY7C1382F manual Truth Table for Read/Write 4, Function CY7C1380D/CY7C1380F

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Truth Table for Read/Write [4, 9]

Function (CY7C1380D/CY7C1380F)

GW

BWE

BWD

BWC

BWB

BWA

Read

H

H

X

X

X

X

Read

H

L

H

H

H

H

Write Byte A – (DQA and DQPA)

H

L

H

H

H

L

Write Byte B – (DQB and DQPB)

H

L

H

H

L

H

Write Bytes B, A

H

L

H

H

L

L

Write Byte C – (DQC and DQPC)

H

L

H

L

H

H

Write Bytes C, A

H

L

H

L

H

L

Write Bytes C, B

H

L

H

L

L

H

Write Bytes C, B, A

H

L

H

L

L

L

Write Byte D – (DQD and DQPD)

H

L

L

H

H

H

Write Bytes D, A

H

L

L

H

H

L

Write Bytes D, B

H

L

L

H

L

H

Write Bytes D, B, A

H

L

L

H

L

L

Write Bytes D, C

H

L

L

L

H

H

Write Bytes D, C, A

H

L

L

L

H

L

Write Bytes D, C, B

H

L

L

L

L

H

Write All Bytes

H

L

L

L

L

L

Write All Bytes

L

X

X

X

X

X

Truth Table for Read/Write [4, 9]

Function (CY7C1382D/CY7C1382F)	GW	BWE	BWB	BWA
Read	H	H	X	X

Read	H	L	H	H

Write Byte A – (DQA and DQPA)	H	L	H	L
Write Byte B – (DQB and DQPB)	H	L	L	H
Write Bytes B, A	H	L	L	L

Write All Bytes	H	L	L	L

Write All Bytes	L	X	X	X

Note

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.

Document #: 38-05543 Rev. *F

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Contents Description 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Pin Definitions Name DescriptionTCK Jtag Pin DefinitionsTMS Functional Overview Single Write Accesses Initiated by Adsp Single Read Accesses Single Write Accesses Initiated by AdscA1 A0 Parameter Description Test Conditions Min Sleep ModeBurst Sequences AddressOperation Add. Used Truth TableFunction CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetClock TAP TimingReserved Parameter Description MinParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Range Ambient Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeEIA/JESD51 CapacitanceThermal Resistance Package5V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadOutput Times Switching Characteristics Over the Operating Range 20Setup Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistoryUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions