Cypress CY7C1380F Identification Register Definitions, Scan Register Sizes, Identification Codes

Page 16

 

 

 

 

 

 

 

 

CY7C1380D, CY7C1382D

 

 

 

 

 

 

 

 

CY7C1380F, CY7C1382F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Field

 

 

 

CY7C1380D/CY7C1380F

CY7C1382D/CY7C1382F

Description

 

 

 

 

 

(512K x 36)

(1 Mbit x 18)

 

 

 

 

 

 

 

 

 

Revision Number (31:29)

 

 

 

000

 

000

Describes the version number.

 

 

 

 

 

 

 

 

 

 

 

 

Device Depth (28:24) [13]

 

 

 

01011

 

01011

Reserved for internal use.

 

 

Device Width (23:18) 119-BGA

 

 

 

101000

101000

Defines the memory type and

 

 

 

 

 

 

 

 

 

 

architecture.

 

Device Width (23:18) 165-FBGA

000000

000000

Defines the memory type and

 

 

 

 

 

 

 

 

 

 

architecture.

 

Cypress Device ID (17:12)

 

 

 

100101

010101

Defines the width and density.

 

 

 

 

 

 

 

 

 

 

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

Allows unique identification of

 

 

 

 

 

 

 

 

 

 

SRAM vendor.

 

ID Register Presence Indicator (0)

1

 

1

Indicates the presence of an ID

 

 

 

 

 

 

 

 

 

 

register.

 

Scan Register Sizes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

 

Bit Size (x36)

Bit Size (x18)

 

 

Instruction

 

 

 

 

 

 

3

3

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass

 

 

 

 

 

 

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

32

32

 

 

 

 

 

 

 

 

 

 

Boundary Scan Order (119-ball BGA package)

 

85

85

 

 

 

 

 

 

 

 

 

 

Boundary Scan Order (165-ball FBGA package)

 

89

89

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Code

 

 

 

 

 

Description

 

 

 

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

Forces all SRAM outputs to High-Z state.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

 

 

This operation does not affect SRAM operations.

 

 

 

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

Forces all SRAM output drivers to a High-Z state.

 

 

 

RESERVED

011

Do Not Use. This instruction is reserved for future use.

 

 

 

 

 

 

 

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

Does not affect SRAM operation.

 

 

 

RESERVED

101

Do Not Use. This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

RESERVED

110

Do Not Use. This instruction is reserved for future use.

 

 

 

 

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

 

 

operations.

 

 

 

 

Note

13. Bit #24 is 1 in the register definitions for both 2.5v and 3.3v versions of this device.

Document #: 38-05543 Rev. *F

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Contents Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Ground for the core of the deviceTMS Pin DefinitionsTCK Jtag Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional OverviewSleep Mode Burst SequencesAddress A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing ReservedParameter Description Min ClockTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistancePackage EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadSetup Times Switching Characteristics Over the Operating Range 20Output Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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