Cypress CY7C1380D, CY7C1380F, CY7C1382F, CY7C1382D Ball BGA Boundary Scan Order 14, Bit # Ball ID

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

119-Ball BGA Boundary Scan Order [14, 15]

Bit #	Ball ID	Bit #	Ball ID	Bit #	Ball ID	Bit #	Ball ID
1	H4	23	F6	45	G4	67	L1

2	T4	24	E7	46	A4	68	M2

3	T5	25	D7	47	G3	69	N1

4	T6	26	H7	48	C3	70	P1

5	R5	27	G6	49	B2	71	K1

6	L5	28	E6	50	B3	72	L2

7	R6	29	D6	51	A3	73	N2

8	U6	30	C7	52	C2	74	P2

9	R7	31	B7	53	A2	75	R3

10	T7	32	C6	54	B1	76	T1

11	P6	33	A6	55	C1	77	R1

12	N7	34	C5	56	D2	78	T2

13	M6	35	B5	57	E1	79	L3

14	L7	36	G5	58	F2	80	R2

15	K6	37	B6	59	G1	81	T3

16	P7	38	D4	60	H2	82	L4

17	N6	39	B4	61	D1	83	N4

18	L6	40	F4	62	E2	84	P4

19	K7	41	M4	63	G2	85	Internal

20	J5	42	A5	64	H1

21	H6	43	K4	65	J3

22	G7	44	E4	66	2K

Notes

14.Balls which are NC (No Connect) are pre-set LOW.

15.Bit# 85 is pre-set HIGH.

Document #: 38-05543 Rev. *F

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Contents Functional Description FeaturesSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name Description Ground for the core of the deviceTCK Jtag Pin DefinitionsTMS Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional OverviewBurst Sequences Sleep ModeAddress A1 A0 Parameter Description Test Conditions MinOperation Add. Used Truth TableFunction CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetReserved TAP TimingParameter Description Min Clock3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Range AmbientThermal Resistance CapacitancePackage EIA/JESD515V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadOutput Times Switching Characteristics Over the Operating Range 20Setup Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistoryUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions