Cypress CY7C1382F, CY7C1382D manual Logic Block Diagram CY7C1380D/CY7C1380F 3 512K x

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							CY7C1380D, CY7C1382D
							CY7C1380F, CY7C1382F
Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36)
A0, A1, A		ADDRESS
		ADDRESS
		REGISTER	2	A[1:0]
			2	A[1:0]
MODE
ADV				Q1
CLK			BURST
			COUNTER
			CLR AND	Q0
ADSC			LOGIC
ADSC
ADSP
		DQ D , DQP D		DQ D ,DQP D
BW D		BYTE		BYTE
		WRITE REGISTER		WRITE DRIVER
		DQ C , DQP C		DQ C , DQP C
BW C		BYTE		BYTE				OUTPUT
		WRITE REGISTER		WRITE DRIVER	MEMORY	SENSE	OUTPUT	OUTPUT	D Q s
		WRITE REGISTER		WRITE DRIVER	MEMORY		OUTPUT	BUFFERS
					ARRAY		REGISTERS	BUFFERS
				DQ B , DQP B	ARRAY	AMPS	REGISTERS	E	DQP A
		DQ B , DQP B				AMPS			DQP A
		DQ B , DQP B							DQP B
BW B		BYTE		BYTE					DQP B
				BYTE					DQP C
				WRITE DRIVER
		WRITE REGISTER		WRITE DRIVER
		WRITE REGISTER							DQP D
									DQP D
		DQ A , DQP A		DQ A , DQP A
		DQ A , DQP A		BYTE
BW A		BYTE		BYTE
BW A		BYTE		WRITE DRIVER
BWE		WRITE REGISTER		WRITE DRIVER
BWE		WRITE REGISTER
GW									INPUT
GW		ENABLE	PIPELINED						REGISTERS
CE	1	REGISTER	PIPELINED
CE	1		ENABLE
CE
	2
	2
CE 3
OE
ZZ		SLEEP
ZZ		CONTROL
		CONTROL
Logic Block Diagram – CY7C1382D/CY7C1382F [3] (1M x 18)
A0, A1, A		ADDRESS
A0, A1, A		REGISTER
		REGISTER
			2

ADV	BURST Q1
CLK	COUNTER AND
	LOGIC
ADSC

BW B

BW A

BWE

GW

CE 1 CE2

CE3

OE

DQ B, DQP B

WRITE REGISTER

DQ A,DQP A

WRITE REGISTER

ENABLE

REGISTER

PIPELINED ENABLE

DQ B, DQP B WRITE DRIVER

DQ A,DQP A WRITE DRIVER

MEMORY	SENSE	OUTPUT
ARRAY

OUTPUT BUFFERS

DQs

DQP A

DQP B

INPUT

ZZ

SLEEP

CONTROL

Note

3. CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE1).

Document #: 38-05543 Rev. *F

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Contents Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Pin Definitions Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the deviceTCK Jtag Pin DefinitionsTMS Single Write Accesses Initiated by Adsc Single Write Accesses Initiated by AdspSingle Read Accesses Functional OverviewAddress Sleep ModeBurst Sequences A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass RegisterParameter Description Min TAP TimingReserved Clock5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Range AmbientPackage CapacitanceThermal Resistance EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadOutput Times Switching Characteristics Over the Operating Range 20Setup Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions