Cypress CY7C1360C, CY7C1362C Truth Table for Read/Write5, Ieee 1149.1 Serial Boundary Scan Jtag

					CY7C1360C
					CY7C1362C
Truth Table for Read/Write[5, 9]
Function (CY7C1362C)	GW	BWE	BW	B		BW	A
Read	H	H	X			X
Read	H	L	H			H
Write Byte A – (DQA and DQPA)	H	L	H			L
Write Byte B – (DQB and DQPB)	H	L	L			H
Write Bytes B, A	H	L	L			L
Write All Bytes	H	L	L			L
Write All Bytes	L	X	X			X

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1360C/CY7C1362C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1360C/CY7C1362C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the

1	TEST-LOGIC
	RESET
	0
0	RUN-TEST/	1	SELECT		1	SELECT		1
	IDLE		DR-SCAN			IR-SCAN
				0			0
			1			1
			CAPTURE-DR			CAPTURE-IR
				0			0
			SHIFT-DR		0	SHIFT-IR		0
				1			1
			EXIT1-DR		1	EXIT1-IR		1
				0			0
			PAUSE-DR		0	PAUSE-IR		0
				1			1
			0			0
			EXIT2-DR			EXIT2-IR
				1			1
			UPDATE-DR			UPDATE-IR
			1	0		1	0

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

rising edge of TCK.

Document #: 38-05540 Rev. *H Page 11 of 31

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