Cypress CY7C1360C Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag, NC/576M, NC/288M

Page 5

CY7C1360C

CY7C1362C

Pin Configurations (continued)

119-Ball BGA Pinout (2 Chip Enables with JTAG)

CY7C1360C (256K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

CE2

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

B

DQB

DQB

BW

ADV

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

BWE

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1362C (512K x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

CE2

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

VSS

NC

DQA

BW

ADV

H

DQB

NC

VSS

VSS

DQA

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

VSS

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

BWE

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05540 Rev. *H

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Contents Logic Block Diagram CY7C1362C 512K x FeaturesFunctional Description1 Cypress Semiconductor CorporationSelection Guide Maximum Access Time Maximum Operating Current250 MHz 200 MHz 166 MHz Unit Maximum Cmos Standby Current Document # 38-05540 Rev. *HCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1360C 256K X CY7C1362C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionNC/576M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/72M NC/36M NC/288MNC/72M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/18M Pin Definitions Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Read Cycle, Continue Burst Next Partial Truth Table for Read/Write5Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Write Cycle, Suspend BurstTest Access Port TAP Disabling the Jtag FeatureTruth Table for Read/Write5 Ieee 1149.1 Serial Boundary Scan JtagPerforming a TAP Reset TAP Controller Block DiagramTAP Registers TAP Instruction SetIdcode TAP TimingTAP DC Electrical Characteristics And Operating Conditions TAP AC Switching Characteristics Over the Operating Range103V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes CY7C1362C 512K x Bit# Ball ID Signal CY7C1360C 256K x Bit# Ball ID SignalBall Fbga Boundary Scan Order NameBall BGA Boundary Scan Order CY7C1362C 512K x Bit# Ball ID Signal NameMaximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient RangeThermal Resistance Capacitance16AC Test Loads and Waveforms 3V I/O Test Load250 200 166 Parameter Description Unit Min Switching Characteristics Over the Operating Range 17Min Max Set-up TimesRead Cycle Timing23 Switching WaveformsBWE BWX ADV Write Cycle Timing23CLZ Read/Write Cycle Timing23, 25DON’T Care ZZ Mode Timing27Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball Pbga 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change