Cypress CY7C1362C, CY7C1360C manual Write Cycle Timing23, Bwe Bwx Adv

Page 22

CY7C1360C

CY7C1362C

Switching Waveforms (continued)

Write Cycle Timing[23, 24]

CLK

ADSP

ADSC

ADDRESS

BWE,

BWX

ADV

Data In (D)

		tCYC
	tCH	tCL
tADS	tADH
		tADS	tADH	ADSC extends burst
		tADS	tADH	tADS	tADH
				tADS	tADH
tAS	tAH
	A1			A2	A3
	Byte write signals are
	ignored for first cycle when				tWES tWEH
	ADSP initiates burst				tWES tWEH

tWES tWEH

tCES	tCEH
								tADVS tADVH
				ADV suspends burst
	tDS tDH
High-Z	D(A1)	D(A2)	D(A2 + 1)	D(A2 + 1)	D(A2 + 2)	D(A2 + 3)	D(A3)	D(A3 + 1)	D(A3 + 2)
	t
	OEHZ

Data Out (Q)

BURST READ	Single WRITE	BURST WRITE
	DON’T CARE	UNDEFINED

Note:

24. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Extended BURST WRITE

Document #: 38-05540 Rev. *H

Page 22 of 31

[+] Feedback

Image 22

Contents Functional Description1 FeaturesLogic Block Diagram CY7C1362C 512K x Cypress Semiconductor Corporation250 MHz 200 MHz 166 MHz Unit Maximum Access Time Maximum Operating CurrentSelection Guide Maximum Cmos Standby Current Document # 38-05540 Rev. *HCY7C1360C 256K X Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1362CNC/72M NC/36M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/288MNC/18M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/72M Pin Definitions Single Write Accesses Initiated by Adsc Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Suspend BurstTruth Table for Read/Write5 Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Registers TAP Controller Block DiagramPerforming a TAP Reset TAP Instruction SetTAP Timing Idcode3V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes Ball Fbga Boundary Scan Order CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal NameCY7C1362C 512K x Bit# Ball ID Signal Name Ball BGA Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance 3V I/O Test LoadMin Max Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing23Write Cycle Timing23 BWE BWX ADVRead/Write Cycle Timing23, 25 CLZZZ Mode Timing27 DON’T CareOrdering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Pbga 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History