Cypress CY7C1362C Pin Configurations Ball Fbga Pinout 3 Chip Enable with Jtag, NC/18M, NC/72M

Page 6

CY7C1360C

CY7C1362C

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip Enable with JTAG)

CY7C1360C (256K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

A

A

NC

CE

1

BW

C

BW

B

CE

3

BWE

ADSC

ADV

B

NC/144M

A

CE2

CLK

A

NC/576M

BW

D

BW

A

GW

OE

ADSP

C

DQPC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC/1G

DQPB

D

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

E

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

F

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

G

DQC

DQC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQB

DQB

H

NC

VSS

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

K

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

L

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

M

DQD

DQD

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

DQA

N

DQPD

NC

VDDQ

VSS

NC

NC/18M

NC

VSS

VDDQ

NC

DQPA

P

NC

NC/72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1362C (512K x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

A

1

B

NC

3

A

A

CE

BW

CE

BWE

ADSC

ADV

B

NC/144M

A

CE2

NC

A

CLK

A

NC/576M

BW

GW

OE

ADSP

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC/1G

DQPA

D

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

E

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

F

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

G

NC

DQB

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQA

H

NC

VSS

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

K

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

L

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

M

DQB

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQA

NC

N

DQPB

NC

VDDQ

VSS

NC

NC/18M

NC

VSS

VDDQ

NC

NC

P

NC

NC/72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

NC/36M

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05540 Rev. *H

Page 6 of 31

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Contents Functional Description1 FeaturesLogic Block Diagram CY7C1362C 512K x Cypress Semiconductor Corporation250 MHz 200 MHz 166 MHz Unit Maximum Access Time Maximum Operating CurrentSelection Guide Maximum Cmos Standby Current Document # 38-05540 Rev. *HPin Configurations Pin Tqfp Pinout 3 Chip Enables a Version CY7C1360C 256K XCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1362CNC/72M NC/36M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/288MPin Configurations Ball Fbga Pinout 3 Chip Enable with Jtag NC/18MNC/72M Pin Definitions Single Write Accesses Initiated by Adsc Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Suspend BurstTruth Table for Read/Write5 Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Registers TAP Controller Block DiagramPerforming a TAP Reset TAP Instruction SetTAP Timing Idcode3V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Ball Fbga Boundary Scan Order CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal NameCY7C1362C 512K x Bit# Ball ID Signal Name Ball BGA Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance 3V I/O Test LoadMin Max Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing23Write Cycle Timing23 BWE BWX ADVRead/Write Cycle Timing23, 25 CLZZZ Mode Timing27 DON’T CareOrdering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Pbga 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History