Cypress CY7C1362C, CY7C1360C manual Soldernotespad Type NON-SOLDER Mask Defined Nsmd

Page 30

CY7C1360C

CY7C1362C

Package Diagrams (continued)

 

 

 

 

 

 

 

 

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BOTTOM VIEW

 

 

 

 

 

 

 

 

 

TOP VIEW

 

 

 

 

 

 

 

 

 

BOTTOM VIEWPIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

TOP VIEW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-0Ø0.06

.25 M C A B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.50

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

(165X)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+0.14

-0.06

 

1

2

3

4

5

6

7

8

9

10

11

11

10

9

8

7

6

5

Ø0.50

(165X)

4

3

2

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+0.14

 

15.00±0.10

15.00±0.10

A

1

2

3

4

5

6

7

8

9

10

11

BA

CB

DC

ED

FE

GF

H

G

15.00±0.10

 

 

J

H

 

K

J

 

 

 

LK

ML

NM

PN

RP R

14.00 15.00±0.10

1.00

7.0014.00

1.00

7.00

11

10

9

8

7

6

5

4

3

2

1A

BA

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP

R

A

0.25 C

A

0.3600.25.3±0C .05

A

B

13.00±0.10

 

 

B

13.00±0.10

 

 

0.53±0.05

1.40 MAX.

0.15 C 1.40 MAX.

0.15 C

C

SEATING PLANE

 

 

SEATING PLANE

 

 

 

 

 

0.36

C

 

 

0.35±0.06

0.35±0.06

 

 

1.00

A

5.00

1.00

 

5.00

 

10.00

 

10.00

B

13.00±0.10

B

13.00±0.10

0.15(4X)

 

0.15(4X)

 

NOTES :

 

SOLDERNOTESPAD TYPE: : NON-SOLDER MASK DEFINED (NSMD)

PACKAGESOLDERW IGHTPAD: 0TYPE.475g: NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCEPACKAGE WEIGHT: MO-216: 0./475gDESIGN 4.6C

PACKAGEJEDECODEREFERENCE: BB0AC : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05540 Rev. *H

Page 30 of 31

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Functional Description1 FeaturesLogic Block Diagram CY7C1362C 512K x Cypress Semiconductor Corporation250 MHz 200 MHz 166 MHz Unit Maximum Access Time Maximum Operating CurrentSelection Guide Maximum Cmos Standby Current Document # 38-05540 Rev. *HPin Configurations Pin Tqfp Pinout 3 Chip Enables a Version CY7C1360C 256K XCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1362CNC/72M NC/36M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/288MPin Configurations Ball Fbga Pinout 3 Chip Enable with Jtag NC/18MNC/72M Pin Definitions Single Write Accesses Initiated by Adsc Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Suspend BurstTruth Table for Read/Write5 Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Registers TAP Controller Block DiagramPerforming a TAP Reset TAP Instruction SetTAP Timing Idcode3V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Ball Fbga Boundary Scan Order CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal NameCY7C1362C 512K x Bit# Ball ID Signal Name Ball BGA Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance 3V I/O Test LoadMin Max Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing23Write Cycle Timing23 BWE BWX ADVRead/Write Cycle Timing23, 25 CLZZZ Mode Timing27 DON’T CareOrdering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Pbga 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History
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