Cypress CY7C1360C, CY7C1362C manual TAP Timing, Idcode

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CY7C1360C

CY7C1362C

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE

UNDEFINED

Document #: 38-05540 Rev. *H

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Contents Logic Block Diagram CY7C1362C 512K x FeaturesFunctional Description1 Cypress Semiconductor CorporationSelection Guide Maximum Access Time Maximum Operating Current250 MHz 200 MHz 166 MHz Unit Maximum Cmos Standby Current Document # 38-05540 Rev. *HCY7C1360C 256K X Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1362C 512K x CY7C1362C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionNC/576M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/72M NC/36M NC/288MNC/18M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/72M Pin Definitions Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Read Cycle, Continue Burst Next Partial Truth Table for Read/Write5Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Write Cycle, Suspend BurstTest Access Port TAP Disabling the Jtag FeatureTruth Table for Read/Write5 Ieee 1149.1 Serial Boundary Scan JtagPerforming a TAP Reset TAP Controller Block DiagramTAP Registers TAP Instruction SetIdcode TAP TimingTAP DC Electrical Characteristics And Operating Conditions TAP AC Switching Characteristics Over the Operating Range103V TAP AC Test Conditions 5V TAP AC Test ConditionsScan Register Sizes Identification Register DefinitionsIdentification Codes CY7C1362C 512K x Bit# Ball ID Signal CY7C1360C 256K x Bit# Ball ID SignalBall Fbga Boundary Scan Order NameBall BGA Boundary Scan Order CY7C1362C 512K x Bit# Ball ID Signal NameMaximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient RangeThermal Resistance Capacitance16AC Test Loads and Waveforms 3V I/O Test Load250 200 166 Parameter Description Unit Min Switching Characteristics Over the Operating Range 17Min Max Set-up TimesRead Cycle Timing23 Switching WaveformsBWE BWX ADV Write Cycle Timing23CLZ Read/Write Cycle Timing23, 25DON’T Care ZZ Mode Timing27Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball Pbga 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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