Cypress CY7C1360C, CY7C1362C manual Read/Write Cycle Timing23, 25, Clz

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CY7C1360C

CY7C1362C

Switching Waveforms (continued)

Read/Write Cycle Timing[23, 25, 26]

			tCYC
CLK
		tCH	tCL
	tADS	tADH
ADSP
ADSC
	tAS	tAH
ADDRESS	A1	A2
BWE,
BWX
	tCES	tCEH
CE
ADV
OE
			tCO

A3 A4

tWES tWEH

tDS tDH

A5 A6

Data In (D)	High-Z	t	tOEHZ
		t	tOEHZ
		CLZ
Data Out (Q)	High-Z	Q(A1)	Q(A2)

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE	BURST READ
DON’T CARE	UNDEFINED

Back-to-Back

WRITEs

Notes:

25.The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC.

26.GW is HIGH.

Document #: 38-05540 Rev. *H

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram CY7C1362C 512K x Functional Description1Maximum Cmos Standby Current Document # 38-05540 Rev. *H Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1360C 256K X CY7C1362C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionNC/288M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/72M NC/36MNC/72M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/18M Pin Definitions Functional Overview Single Read AccessesSingle Write Accesses Initiated by Adsp Single Write Accesses Initiated by AdscZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Write Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Continue Burst Next Read Cycle, Suspend BurstIeee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Truth Table for Read/Write5TAP Instruction Set TAP Controller Block DiagramPerforming a TAP Reset TAP RegistersIdcode TAP Timing5V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Name CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal Ball Fbga Boundary Scan OrderBall BGA Boundary Scan Order CY7C1362C 512K x Bit# Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating Range3V I/O Test Load Capacitance16Thermal Resistance AC Test Loads and WaveformsSet-up Times Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Min MaxRead Cycle Timing23 Switching WaveformsBWE BWX ADV Write Cycle Timing23CLZ Read/Write Cycle Timing23, 25DON’T Care ZZ Mode Timing27Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball Pbga 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change