Cypress manual CY7C1360C CY7C1362C

Page 27

CY7C1360C

CY7C1362C

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

250	CY7C1360C-250AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Commercial
			(3 Chip Enable)
	CY7C1362C-250AXC		(3 Chip Enable)
	CY7C1362C-250AXC

	CY7C1360C-250AJXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
			(2 Chip Enable)
	CY7C1362C-250AJXC		(2 Chip Enable)
	CY7C1362C-250AJXC

	CY7C1360C-250BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1362C-250BGC

	CY7C1360C-250BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1362C-250BGXC

	CY7C1360C-250BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1362C-250BZC

	CY7C1360C-250BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1362C-250BZXC

	CY7C1360C-250AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Industrial
			(3 Chip Enable)
	CY7C1362C-250AXI		(3 Chip Enable)
	CY7C1362C-250AXI

	CY7C1360C-250AJXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
			(2 Chip Enable)
	CY7C1362C-250AJXI		(2 Chip Enable)
	CY7C1362C-250AJXI

	CY7C1360C-250BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1362C-250BGI

	CY7C1360C-250BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1362C-250BGXI

	CY7C1360C-250BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1362C-250BZI

	CY7C1360C-250BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1362C-250BZXI

Document #: 38-05540 Rev. *H

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram CY7C1362C 512K x Functional Description1Maximum Cmos Standby Current Document # 38-05540 Rev. *H Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz UnitPin Configurations Pin Tqfp Pinout 3 Chip Enables a Version CY7C1360C 256K XCY7C1362C 512K x CY7C1362C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionNC/288M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/72M NC/36MPin Configurations Ball Fbga Pinout 3 Chip Enable with Jtag NC/18MNC/72M Pin Definitions Functional Overview Single Read AccessesSingle Write Accesses Initiated by Adsp Single Write Accesses Initiated by AdscInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Write Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Continue Burst Next Read Cycle, Suspend BurstIeee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Truth Table for Read/Write5TAP Instruction Set TAP Controller Block DiagramPerforming a TAP Reset TAP RegistersIdcode TAP Timing5V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test ConditionsIdentification Register Definitions Scan Register SizesIdentification Codes Name CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal Ball Fbga Boundary Scan OrderBall BGA Boundary Scan Order CY7C1362C 512K x Bit# Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating Range3V I/O Test Load Capacitance16Thermal Resistance AC Test Loads and WaveformsSet-up Times Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Min MaxRead Cycle Timing23 Switching WaveformsBWE BWX ADV Write Cycle Timing23CLZ Read/Write Cycle Timing23, 25DON’T Care ZZ Mode Timing27Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball Pbga 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change