Cypress CY7C1362C, CY7C1360C manual Functional Overview, Single Read Accesses

		CY7C1360C
		CY7C1362C
Pin Definitions (continued)
Name	I/O	Description
TDI	JTAG serial input	Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
	Synchronous	not being utilized, this pin can be disconnected or connected to VDD. This pin is not available
		on TQFP packages.
TMS	JTAG serial input	Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
	Synchronous	not being utilized, this pin can be disconnected or connected to VDD. This pin is not available
		on TQFP packages.
TCK	JTAG-	Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
	Clock	connected to VSS. This pin is not available on TQFP packages.
NC	–	No Connects. Not internally connected to the die
NC (18,36,	–	These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
72, 144, 288,		288M, 576M, and 1G densities.
576, 1G)

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.8 ns (250-MHz device).

The CY7C1360C/CY7C1362C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3[2] are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs

(A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.8 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the

access. After the first cycle of the access, the outputs are

controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3[2] are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corre- sponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BWX signals. The CY7C1360C/CY7C1362C provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations.

Because the CY7C1360C/CY7C1362C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automati- cally tri-stated whenever a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3[2] are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is

Document #: 38-05540 Rev. *H Page 8 of 31

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