Cypress manual CY7C1360C CY7C1362C

Page 26

CY7C1360C

CY7C1362C

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

200	CY7C1360C-200AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Commercial
			(3 Chip Enable)
	CY7C1362C-200AXC		(3 Chip Enable)
	CY7C1362C-200AXC

	CY7C1360C-200AJXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
			(2 Chip Enable)
	CY7C1362C-200AJXC		(2 Chip Enable)
	CY7C1362C-200AJXC

	CY7C1360C-200BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1362C-200BGC

	CY7C1360C-200BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1362C-200BGXC

	CY7C1360C-200BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1362C-200BZC

	CY7C1360C-200BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1362C-200BZXC

	CY7C1360C-200AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Industrial
			(3 Chip Enable)
	CY7C1362C-200AXI		(3 Chip Enable)
	CY7C1362C-200AXI

	CY7C1360C-200AJXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
			(2 Chip Enable)
	CY7C1362C-200AJXI		(2 Chip Enable)
	CY7C1362C-200AJXI

	CY7C1360C-200BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1362C-200BGI

	CY7C1360C-200BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1362C-200BGXI

	CY7C1360C-200BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1362C-200BZI

	CY7C1360C-200BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1362C-200BZXI

Document #: 38-05540 Rev. *H

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Contents Functional Description1 FeaturesLogic Block Diagram CY7C1362C 512K x Cypress Semiconductor Corporation250 MHz 200 MHz 166 MHz Unit Maximum Access Time Maximum Operating CurrentSelection Guide Maximum Cmos Standby Current Document # 38-05540 Rev. *HCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1360C 256K X Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1362CNC/72M NC/36M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/288MNC/72M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/18M Pin Definitions Single Write Accesses Initiated by Adsc Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Suspend BurstTruth Table for Read/Write5 Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Registers TAP Controller Block DiagramPerforming a TAP Reset TAP Instruction SetTAP Timing Idcode3V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Ball Fbga Boundary Scan Order CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal NameCY7C1362C 512K x Bit# Ball ID Signal Name Ball BGA Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance 3V I/O Test LoadMin Max Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing23Write Cycle Timing23 BWE BWX ADVRead/Write Cycle Timing23, 25 CLZZZ Mode Timing27 DON’T CareOrdering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Pbga 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History