Cypress CY7C1362C, CY7C1360C manual Selection Guide, MHz 200 MHz 166 MHz Unit

Page 2

									CY7C1360C
									CY7C1362C
.
Logic Block Diagram – CY7C1360C (256K x 36)
A0, A1, A	ADDRESS
	ADDRESS
	REGISTER		2	A[1:0]
			2	A[1:0]
MODE
ADV				Q1
CLK			BURST
		COUNTER
		CLR	AND	Q0
ADSC			LOGIC
ADSC
ADSP
	DQD ,DQPD			DQD ,DQPD
BWD	BYTE			BYTE
	WRITE REGISTER			WRITE DRIVER
	DQC ,DQPC			DQC ,DQPC
BWC	BYTE			BYTE				OUTPUT
	WRITE REGISTER			WRITE DRIVER	MEMORY	SENSE	OUTPUT	OUTPUT	DQs
	WRITE REGISTER			WRITE DRIVER	MEMORY		OUTPUT	BUFFERS
					ARRAY		REGISTERS	BUFFERS
				DQB ,DQPB	ARRAY	AMPS	REGISTERS	E	DQPA
	DQB ,DQPB					AMPS			DQPA
	DQB ,DQPB								DQPB
BWB	BYTE			BYTE					DQPB
				BYTE					DQPC
				WRITE DRIVER
	WRITE REGISTER			WRITE DRIVER
	WRITE REGISTER								DQPD
									DQPD
	DQA ,DQPA			DQA ,DQPA
	DQA ,DQPA			BYTE
BWA	BYTE			BYTE
BWA	BYTE			WRITE DRIVER
BWE	WRITE REGISTER			WRITE DRIVER
BWE	WRITE REGISTER
GW									INPUT
GW	ENABLE	PIPELINED							REGISTERS
CE1	REGISTER	PIPELINED
CE1		ENABLE
CE2


CE3
OE
ZZ	SLEEP
ZZ	CONTROL
	CONTROL

Selection Guide

	250 MHz	200 MHz	166 MHz	Unit
Maximum Access Time	2.8	3.0	3.5	ns

Maximum Operating Current	250	220	180	mA

Maximum CMOS Standby Current	40	40	40	mA

Document #: 38-05540 Rev. *H

Page 2 of 31

[+] Feedback

Image 2

Contents Functional Description1 FeaturesLogic Block Diagram CY7C1362C 512K x Cypress Semiconductor Corporation250 MHz 200 MHz 166 MHz Unit Maximum Access Time Maximum Operating CurrentSelection Guide Maximum Cmos Standby Current Document # 38-05540 Rev. *HCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1360C 256K X Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1362CNC/72M NC/36M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/288MNC/72M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/18M Pin Definitions Single Write Accesses Initiated by Adsc Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Suspend BurstTruth Table for Read/Write5 Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Registers TAP Controller Block DiagramPerforming a TAP Reset TAP Instruction SetTAP Timing Idcode3V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test ConditionsIdentification Codes Identification Register DefinitionsScan Register Sizes Ball Fbga Boundary Scan Order CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal NameCY7C1362C 512K x Bit# Ball ID Signal Name Ball BGA Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range14Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance16Thermal Resistance 3V I/O Test LoadMin Max Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing23Write Cycle Timing23 BWE BWX ADVRead/Write Cycle Timing23, 25 CLZZZ Mode Timing27 DON’T CareOrdering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Pbga 14 x 22 x 2.4 mm 90±0.05Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1362C

Logic Block Diagram – CY7C1360C (256K x 36)

BWC

Selection Guide

250 MHz

200 MHz

166 MHz

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Document #: 38-05540 Rev. *H