Cypress CY7C1513V18 Logic Block Diagram CY7C1511V18, Logic Block Diagram CY7C1526V18, Doff

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Logic Block Diagram (CY7C1511V18)

8

D[7:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
NWS
	[1:0]

Write Add. Decode

Write	Write	Write	Write
Reg	Reg	Reg	Reg
2M x	2M x	2M x	2M x	Decode
8 Array	8 Array	8 Array	8 Array	Read Add.
Read Data Reg.
	32	16
					Reg.
		16
					Reg.

Address					21		A(20:0)
Register
	Control					RPS
		Logic				C
						C
									CQ
								CQ
				8
			Reg.
				8		8
				8				Q[7:0]
				8

Logic Block Diagram (CY7C1526V18)

9

D[8:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[0]

Write Add. Decode

Write	Write	Write	Write
Reg	Reg	Reg	Reg
2M x	2M x	2M x	2M x	Decode
9 Array	9 Array	9 Array	9 Array	Read Add.
Read Data Reg.
	36	18
					Reg.
		18
					Reg.

Address					21		A(20:0)
Register
	Control					RPS
		Logic				C
						C
									CQ
								CQ
				9
			Reg.
				9		9
				9				Q[8:0]
				9

Document Number: 38-05363 Rev. *F Page 2 of 32

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