Cypress CY7C1511V18, CY7C1526V18 manual CY7C1513V18 4M x, Wps Bws, CY7C1515V18 2M x

Page 5

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Pin Configuration (continued)

The pin configuration for CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 follow. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1513V18 (4M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

VSS/144M

A

1

NC/288M

A

A

CQ

CQ

WPS

BWS

K

RPS

B

NC

Q9

D9

A

NC

K

0

A

NC

NC

Q8

BWS

C

NC

NC

D10

VSS

A

NC

A

VSS

NC

Q7

D8

D

NC

D11

Q10

VSS

VSS

VSS

VSS

VSS

NC

NC

D7

E

NC

NC

Q11

VDDQ

VSS

VSS

VSS

VDDQ

NC

D6

Q6

F

NC

Q12

D12

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

Q5

G

NC

D13

Q13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

D5

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

D14

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q4

D4

K

NC

NC

Q14

VDDQ

VDD

VSS

VDD

VDDQ

NC

D3

Q3

L

NC

Q15

D15

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q2

M

NC

NC

D16

VSS

VSS

VSS

VSS

VSS

NC

Q1

D2

N

NC

D17

Q16

VSS

A

A

A

VSS

NC

NC

D1

P

NC

NC

Q17

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1515V18 (2M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

VSS/288M

A

2

1

A

VSS/144M

CQ

CQ

WPS

BWS

K

BWS

RPS

B

Q27

Q18

D18

A

3

K

0

A

D17

Q17

Q8

BWS

BWS

C

D27

Q28

D19

VSS

A

NC

A

VSS

D16

Q7

D8

D

D28

D20

Q19

VSS

VSS

VSS

VSS

VSS

Q16

D15

D7

E

Q29

D29

Q20

VDDQ

VSS

VSS

VSS

VDDQ

Q15

D6

Q6

F

Q30

Q21

D21

VDDQ

VDD

VSS

VDD

VDDQ

D14

Q14

Q5

G

D30

D22

Q22

VDDQ

VDD

VSS

VDD

VDDQ

Q13

D13

D5

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

D31

Q31

D23

VDDQ

VDD

VSS

VDD

VDDQ

D12

Q4

D4

K

Q32

D32

Q23

VDDQ

VDD

VSS

VDD

VDDQ

Q12

D3

Q3

L

Q33

Q24

D24

VDDQ

VSS

VSS

VSS

VDDQ

D11

Q11

Q2

M

D33

Q34

D25

VSS

VSS

VSS

VSS

VSS

D10

Q1

D2

N

D34

D26

Q25

VSS

A

A

A

VSS

Q10

D9

D1

P

Q35

D35

Q26

A

A

C

A

A

Q9

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Document Number: 38-05363 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1511V18Logic Block Diagram CY7C1526V18 Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1511V18 8M x CY7C1526V18 8M xCY7C1515V18 2M x CY7C1513V18 4M xWPS BWS Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Single Clock ModeRead Operations Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksTruth Table Application ExampleSram #1 OperationComments Write Cycle DescriptionsNWS1 BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN no Submission ORIG. Description of Change Date Document HistoryDocument Number Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/AESA Pyrs