Cypress CY7C1511V18, CY7C1513V18, CY7C1526V18, CY7C1515V18 manual 167

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CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
167	CY7C1511V18-167BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1526V18-167BZC

	CY7C1513V18-167BZC

	CY7C1515V18-167BZC

	CY7C1511V18-167BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1526V18-167BZXC

	CY7C1513V18-167BZXC

	CY7C1515V18-167BZXC

	CY7C1511V18-167BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1526V18-167BZI

	CY7C1513V18-167BZI

	CY7C1515V18-167BZI

	CY7C1511V18-167BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1526V18-167BZXI

	CY7C1513V18-167BZXI

	CY7C1515V18-167BZXI

Document Number: 38-05363 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1511V18Logic Block Diagram CY7C1526V18 Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1511V18 8M x CY7C1526V18 8M xCY7C1515V18 2M x CY7C1513V18 4M xWPS BWS Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Single Clock ModeRead Operations Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksTruth Table Application ExampleSram #1 OperationComments Write Cycle DescriptionsNWS1 BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN no Submission ORIG. Description of Change Date Document HistoryDocument Number Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/AESA Pyrs