Cypress CY7C1515V18, CY7C1513V18, CY7C1511V18, CY7C1526V18 manual Document History, Document Number

Page 31

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Document History Page

Document Title: CY7C1511V18/CY7C1526V18/CY7C1513V18/CY7C1515V18, 72-Mbit QDR™-II SRAM 4-Word Burst Archi-

tecture

 

 

 

 

Document Number: 38-05363

 

 

REV.

ECN NO.

SUBMISSION

ORIG. OF

DESCRIPTION OF CHANGE

DATE

CHANGE

**

226981

See ECN

DIM

New Data Sheet

 

 

 

 

 

*A

257089

See ECN

NJY

Modified JTAG ID code for x9 option in the ID register definition on page 20 of

 

 

 

 

the data sheet

 

 

 

 

Included thermal values

 

 

 

 

Modified capacitance values table: included capacitance values for x8, x18

 

 

 

 

and x36 options

*B

319496

See ECN

SYT

Removed CY7C1526V18 from the title

 

 

 

 

Included 300-MHz Speed Bin

 

 

 

 

Added footnote #1 and accordingly edited the VSS/144M And VSS/288M on

 

 

 

 

the Pin Definitions table

 

 

 

 

Added Industrial temperature grade

 

 

 

 

Replaced TBDs for IDD and ISB1 for 300 MHz, 250 MHz, 200 MHz and 167

 

 

 

 

MHz speed grades

 

 

 

 

Changed the CIN from 5 pF to 5.5 pF and CO from 7 pF to 8 pF in the

 

 

 

 

Capacitance Table

 

 

 

 

Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS

 

 

 

 

TRI-STATE on Page 17

 

 

 

 

Removed the capacitance value column for the x9 option from Capacitance

 

 

 

 

Table

 

 

 

 

Added lead-free product information

 

 

 

 

Updated the Ordering Information by Shading and unshading as per avail-

 

 

 

 

ability

*C

403231

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Added CY7C1526V18 part number to the title

 

 

 

 

Added 278-MHz speed Bin

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed C/C Pin Description in the features section and Pin Description

 

 

 

 

Added power-up sequence details and waveforms

 

 

 

 

Added foot notes #16, 17, 18 on page# 19

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current

 

 

 

 

on page# 20

 

 

 

 

Modified the IDD and ISB values

 

 

 

 

Modified test condition in Footnote #19 on page # 20 from VDDQ < VDD to

 

 

 

 

VDDQ < VDD

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated Ordering Information Table

*D

467290

See ECN

NXR

Modified the ZQ Definition from Alternately, this pin can be connected directly

 

 

 

 

to VDD to Alternately, this pin can be connected directly to VDDQ

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD

 

 

 

 

Changed tTCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns,

 

 

 

 

changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed

 

 

 

 

tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table

 

 

 

 

Modified Power-Up waveform

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied

 

 

 

 

from –10°C to +85°C to –55°C to +125°C

 

 

 

 

Added additional notes in the AC parameter section

 

 

 

 

Modified AC Switching Waveform

 

 

 

 

Updated the Typo in the AC Switching Characteristics Table

 

 

 

 

Updated the Ordering Information Table

Document Number: 38-05363 Rev. *F

 

Page 31 of 32

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Image 31
Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1526V18 Logic Block Diagram CY7C1511V18Doff Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18CY7C1526V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1511V18 8M xWPS BWS CY7C1513V18 4M xCY7C1515V18 2M x Pin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toWrite Operations Single Clock ModeFunctional Overview Read OperationsEcho Clocks Concurrent TransactionsDepth Expansion Programmable ImpedanceOperation Application ExampleTruth Table Sram #1BWS0 Write Cycle DescriptionsComments NWS1BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument Number Document HistoryREV ECN no Submission ORIG. Description of Change Date Pyrs Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/AESA