Cypress CY7C1515V18 Referenced with Respect to, TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag

Page 7

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18, CY7C1526V18

 

 

 

 

 

 

 

 

 

 

 

CY7C1513V18, CY7C1515V18

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

 

Pin Description

 

CQ

Echo Clock

 

CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

 

 

 

 

 

 

for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings

 

 

 

 

 

 

for the echo clocks are shown in the Switching Characteristics on page 24.

 

 

 

 

Echo Clock

 

 

Referenced with Respect to

 

. This is a free running clock and is synchronized to the input clock

 

CQ

 

 

 

CQ

C

 

 

 

 

 

 

for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings

 

 

 

 

 

 

for the echo clocks are shown in the Switching Characteristics on page 24.

 

ZQ

Input

 

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

 

 

 

 

 

 

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

 

 

 

 

 

 

between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the

 

 

 

 

 

 

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

 

 

 

Input

 

DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

 

DOFF

 

 

 

 

 

 

timings in the DLL turned off operation differs from those listed in this data sheet.

 

TDO

Output

 

TDO for JTAG.

 

 

 

 

 

 

TCK

Input

 

TCK Pin for JTAG.

 

 

 

 

 

 

TDI

Input

 

TDI Pin for JTAG.

 

 

 

 

 

 

TMS

Input

 

TMS Pin for JTAG.

 

 

 

 

 

 

NC

N/A

 

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

 

VSS/144M

N/A

 

Address expansion for 144M. Can be tied to any voltage level.

 

VSS/288M

N/A

 

Address expansion for 288M. Can be tied to any voltage level.

 

VREF

Input-

 

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

 

 

 

 

Reference

 

measurement points.

 

VDD

Power Supply

 

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

 

Ground for the Device.

 

VDDQ

Power Supply

 

Power Supply Inputs for the Outputs of the Device.

Document Number: 38-05363 Rev. *F

Page 7 of 32

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1526V18 Logic Block Diagram CY7C1511V18Doff Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18CY7C1526V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1511V18 8M xWPS BWS CY7C1513V18 4M xCY7C1515V18 2M x Pin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toWrite Operations Single Clock ModeFunctional Overview Read OperationsEcho Clocks Concurrent TransactionsDepth Expansion Programmable ImpedanceOperation Application ExampleTruth Table Sram #1BWS0 Write Cycle DescriptionsComments NWS1BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument Number Document HistoryREV ECN no Submission ORIG. Description of Change Date Pyrs Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/AESA