Cypress CY7C1526V18, CY7C1513V18, CY7C1511V18 manual Package Diagram, Ball Fbga 15 x 17 x 1.4 mm

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CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Package Diagram

Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195

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Document Number: 38-05363 Rev. *F

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1511V18 Logic Block Diagram CY7C1526V18Doff Logic Block Diagram CY7C1513V18 Logic Block Diagram CY7C1515V18CY7C1511V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1526V18 8M xCY7C1513V18 4M x WPS BWSCY7C1515V18 2M x Pin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagRead Operations Single Clock ModeFunctional Overview Write OperationsProgrammable Impedance Concurrent TransactionsDepth Expansion Echo ClocksSram #1 Application ExampleTruth Table OperationNWS1 Write Cycle DescriptionsComments BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 28, 29Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History Document NumberREV ECN no Submission ORIG. Description of Change Date VKN/AESA Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Pyrs