Cypress CY7C1511V18, CY7C1513V18, CY7C1526V18 manual Parameter Min Max Output Times, DLL Timing

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Switching Characteristics (continued)

Over the Operating Range [22, 23]

Cypress

Consortium

Description

300 MHz

278 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Output Times

tCO

tCHQV

C/C

Clock Rise (or K/K in single

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50

ns

clock mode) to Data Valid

tDOH

tCHQX

–0.45

–

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

Data Output Hold after Output C/C

Clock Rise (Active to Active)

tCCQO

tCHCQV

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50

ns

C/C

tCQOH

tCHCQX

Clock

–0.45

–

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

Echo Clock Hold after C/C

Rise

tCQD

tCQHQV

Echo Clock High to Data Valid

0.27

0.27

0.30

0.35

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.27

–

–0.27

–

–0.30

–

–0.35

–

–0.40

–

ns

tCHZ

tCHQZ

Rise to High-Z

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50

ns

Clock (C/C)

(Active to High-Z) [26, 27]

tCLZ

tCHQX1

Rise to Low-Z [26, 27]

–0.45

–

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

Clock (C/C)

DLL Timing

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

1024

–

1024

–

1024

–

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

30

30

30

30

ns

Notes

26.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms on page 23. Transition is measured ± 100 mV from steady-state voltage.

27.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document Number: 38-05363 Rev. *F Page 25 of 32

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