Cypress CY7C1515V18, CY7C1513V18, CY7C1511V18 manual Write Cycle Descriptions, Comments, NWS1, BWS0

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CY7C1511V18, CY7C1526V18

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1513V18, CY7C1515V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

The write cycle description table for CY7C1511V18 and CY7C1513V18 follows. [2, 10]

 

 

 

 

BWS

0/

 

BWS

1/

K

 

 

 

 

 

Comments

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1513V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

L

L-H

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1513V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

H

L–H

 

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

 

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

L–H

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

 

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L–H

 

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

 

remains unaltered.

 

H

 

L

L–H

During the data portion of a write sequence :

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

 

remains unaltered.

 

H

 

H

L–H

 

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1526V18 follows. [2, 10]

BWS0

K

K

Comments

L

L–H

During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

L–H

During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Note

10.Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.

Document Number: 38-05363 Rev. *F

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1511V18Logic Block Diagram CY7C1526V18 Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18CY7C1526V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1511V18 8M xCY7C1515V18 2M x CY7C1513V18 4M xWPS BWS Pin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toWrite Operations Single Clock ModeFunctional Overview Read OperationsEcho Clocks Concurrent TransactionsDepth Expansion Programmable ImpedanceOperation Application ExampleTruth Table Sram #1BWS0 Write Cycle DescriptionsComments NWS1BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN no Submission ORIG. Description of Change Date Document HistoryDocument Number Pyrs Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/AESA