Cypress CY7C1511V18 manual Logic Block Diagram CY7C1513V18, Logic Block Diagram CY7C1515V18

Page 3

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Logic Block Diagram (CY7C1513V18)

D[17:0]

20Address

A(19:0) Register

K CLK

Gen.

DOFF

VREF		Control

WPS
		Logic

BWS
	[1:0]

Write Add. Decode

Write

Address

A(19:0)

Reg

1M x

Decode

18Array

ReadAdd.

Logic

Control

RPS

Read Data Reg.

Reg.

Q[17:0]

Reg.

Logic Block Diagram (CY7C1515V18)

D[35:0]

19Address

A(18:0) Register

K CLK

Gen.

DOFF

VREF		Control

WPS
		Logic

BWS
	[3:0]

Write Add. Decode

Write

Address

A(18:0)

Reg

512K x

Decode

36Array

ReadAdd.

Logic

Control

RPS

Read Data Reg.

144

Reg.

Q[35:0]

Reg.

Document Number: 38-05363 Rev. *F

Page 3 of 32

[+] Feedback

Image 3

Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1511V18 Logic Block Diagram CY7C1526V18Doff Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18CY7C1526V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1511V18 8M xCY7C1513V18 4M x WPS BWSCY7C1515V18 2M x Pin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toWrite Operations Single Clock ModeFunctional Overview Read OperationsEcho Clocks Concurrent TransactionsDepth Expansion Programmable ImpedanceOperation Application ExampleTruth Table Sram #1BWS0 Write Cycle DescriptionsComments NWS1BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitLOW Switching CharacteristicsParameter Min Max HighDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History Document NumberREV ECN no Submission ORIG. Description of Change Date Pyrs Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/AESA