Cypress CY7C1511V18, CY7C1513V18, CY7C1526V18 Maximum Ratings, DC Electrical Characteristics

Page 21

CY7C1511V18, CY7C1526V18 CY7C1513V18, CY7C1515V18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [13]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch-up Current

...................................................

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [17]

VDDQ [17]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [14]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 18

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 19

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.3

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

5

 

5

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

5

 

5

μA

VREF

Input Reference Voltage [20]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [21]

VDD Operating Supply

VDD = Max,

300MHz

(x8)

 

 

930

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

940

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

1020

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1230

 

 

 

 

278MHz

(x8)

 

 

865

mA

 

 

 

 

(x9)

 

 

870

 

 

 

 

 

(x18)

 

 

950

 

 

 

 

 

(x36)

 

 

1140

 

 

 

 

250MHz

(x8)

 

 

790

mA

 

 

 

 

(x9)

 

 

795

 

 

 

 

 

(x18)

 

 

865

 

 

 

 

 

(x36)

 

 

1040

 

Notes

17.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

18.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

19.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

20.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

21.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 38-05363 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1511V18 Logic Block Diagram CY7C1526V18Doff Logic Block Diagram CY7C1515V18 Logic Block Diagram CY7C1513V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1511V18 8M x CY7C1526V18 8M xCY7C1513V18 4M x WPS BWSCY7C1515V18 2M x Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Single Clock ModeRead Operations Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksTruth Table Application ExampleSram #1 OperationComments Write Cycle DescriptionsNWS1 BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesRead/Write/Deselect Sequence 28, 29 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History Document NumberREV ECN no Submission ORIG. Description of Change Date Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/AESA Pyrs