Cypress CY7C1513V18, CY7C1511V18, CY7C1526V18, CY7C1515V18 manual BWS0 BWS1 BWS2 BWS3

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CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Write Cycle Descriptions

The write cycle description table for CY7C1515V18 follows. [2, 10]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

During the Data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

 

L

 

L

L–H

During the Data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

H

 

H

L–H

 

During the Data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

L–H

During the Data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

During the Data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

L

 

H

 

H

L–H

During the Data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

H

 

L

 

H

L–H

 

During the Data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

L

 

H

L–H

During the Data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

H

 

L

L–H

 

During the Data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

L–H

During the Data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 38-05363 Rev. *F

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1511V18 Logic Block Diagram CY7C1526V18Doff Logic Block Diagram CY7C1513V18 Logic Block Diagram CY7C1515V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1511V18 8M x CY7C1526V18 8M xCY7C1513V18 4M x WPS BWSCY7C1515V18 2M x Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagSingle Clock Mode Functional OverviewRead Operations Write OperationsConcurrent Transactions Depth ExpansionProgrammable Impedance Echo ClocksApplication Example Truth TableSram #1 OperationWrite Cycle Descriptions CommentsNWS1 BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Parameter Min MaxHigh LOWParameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 28, 29Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History Document NumberREV ECN no Submission ORIG. Description of Change Date Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsVKN/AESA Pyrs