Cypress CY7C1526V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1511V18	CY7C1526V18	CY7C1513V18	CY7C1515V18	Description
		CY7C1511V18	CY7C1526V18	CY7C1513V18	CY7C1515V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010011011000100	11010011011001100	11010011011010100	11010011011100100	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document Number: 38-05363 Rev. *F

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1511V18 Logic Block Diagram CY7C1526V18Doff Logic Block Diagram CY7C1513V18 Logic Block Diagram CY7C1515V18CY7C1511V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1526V18 8M xCY7C1513V18 4M x WPS BWSCY7C1515V18 2M x Pin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagRead Operations Single Clock ModeFunctional Overview Write OperationsProgrammable Impedance Concurrent TransactionsDepth Expansion Echo ClocksSram #1 Application ExampleTruth Table OperationNWS1 Write Cycle DescriptionsComments BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 28, 29Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History Document NumberREV ECN no Submission ORIG. Description of Change Date VKN/AESA Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Pyrs