Cypress CY7C1526V18, CY7C1513V18, CY7C1511V18, CY7C1515V18 manual AC Electrical Characteristics

Page 22

CY7C1511V18, CY7C1526V18

CY7C1513V18, CY7C1515V18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [14]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

IDD [21]

VDD Operating Supply

VDD = Max,

200MHz

(x8)

 

 

655

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

660

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

715

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

850

 

 

 

 

167MHz

(x8)

 

 

570

mA

 

 

 

 

(x9)

 

 

575

 

 

 

 

 

(x18)

 

 

615

 

 

 

 

 

(x36)

 

 

725

 

ISB1

Automatic Power down

Max VDD,

300MHz

(x8)

 

 

400

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

 

 

(x9)

 

 

400

 

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

(x18)

 

 

400

 

 

 

f = fMAX = 1/tCYC, Inputs

 

 

 

 

 

 

Static

 

(x36)

 

 

400

 

 

 

 

278MHz

(x8)

 

 

390

mA

 

 

 

 

(x9)

 

 

390

 

 

 

 

 

(x18)

 

 

390

 

 

 

 

 

(x36)

 

 

390

 

 

 

 

250MHz

(x8)

 

 

380

mA

 

 

 

 

(x9)

 

 

380

 

 

 

 

 

(x18)

 

 

380

 

 

 

 

 

(x36)

 

 

380

 

 

 

 

200MHz

(x8)

 

 

360

mA

 

 

 

 

(x9)

 

 

360

 

 

 

 

 

(x18)

 

 

360

 

 

 

 

 

(x36)

 

 

360

 

 

 

 

167MHz

(x8)

 

 

340

mA

 

 

 

 

(x9)

 

 

340

 

 

 

 

 

(x18)

 

 

340

 

 

 

 

 

(x36)

 

 

340

 

AC Electrical Characteristics

Over the Operating Range [13]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

V

VIL

Input LOW Voltage

 

VREF – 0.2

V

Document Number: 38-05363 Rev. *F

Page 22 of 32

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1526V18 Logic Block Diagram CY7C1511V18Doff Logic Block Diagram CY7C1513V18 Logic Block Diagram CY7C1515V18CY7C1511V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1526V18 8M xWPS BWS CY7C1513V18 4M xCY7C1515V18 2M x Pin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagRead Operations Single Clock ModeFunctional Overview Write OperationsProgrammable Impedance Concurrent TransactionsDepth Expansion Echo ClocksSram #1 Application ExampleTruth Table OperationNWS1 Write Cycle DescriptionsComments BWS0BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsParameter Min Max LOWParameter Min Max Output Times DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 28, 29Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument Number Document HistoryREV ECN no Submission ORIG. Description of Change Date VKN/AESA Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Pyrs