Cypress CY7C1470BV33, CY7C1474BV33, CY7C1472BV33 manual TAP Timing

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CY7C1470BV33 CY7C1472BV33, CY7C1474BV33

possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not imple- mented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Figure 4. TAP Timing

1		2
Test Clock
(TCK )				tTH
				tTH

tTM SS			tTM SH

Test M ode Select (TM S)

tTDIS tTDIH

Test Data-In (TDI)

Test Data-Out (TDO)

3	4	5	6
tTL	tCY C

tTDOV

tTDOX

DON’T CA RE

UNDEFINED

Document #: 001-15031 Rev. *C

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Contents Description 250 MHz 200 MHz 167 MHz Unit Functional DescriptionSelection Guide Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1470BV33 2M x Logic Block Diagram CY7C1472BV33 4M xLogic Block Diagram CY7C1474BV33 1M x ADV/LDPin Configurations Pin Tqfp PinoutTDI TDO CENNC/1G CE2 CLK ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Pin Definitions Pin Name IO Type Pin Description Byte Write Select Inputs, Active LOW. Qualified withFunctional Overview ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitTruth Table Operation Address UsedFunction CY7C1472BV33 Partial Write Cycle DescriptionFunction CY7C1470BV33 BW d BW c BW b BW a Function CY7C1474BV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing Output Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions GND VIN VddqScan Register Sizes Register Name Bit Size Identification Codes Instruction DescriptionBoundary Scan Exit Order 2M x Bit # Ball ID Boundary Scan Exit Order 4M x Bit # Ball IDE10 Boundary Scan Exit Order 1M xBit # Ball ID V10Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description 250 200 167 Unit Min Max Switching CharacteristicsSetup Times Data Switching WaveformsADV/LD Address A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN