Cypress manual Partial Write Cycle Description, Function CY7C1470BV33 BW d BW c BW b BW a

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 5. Partial Write Cycle Description

The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.[1, 2, 3, 8]

Function (CY7C1470BV33)

WE

BWd

BWc

BWb

BWa

Read

H

X

X

X

X

Write – No bytes written

L

H

H

H

H

Write Byte a – (DQa and DQPa)

L

H

H

H

L

Write Byte b – (DQb and DQPb)

L

H

H

L

H

Write Bytes b, a

L

H

H

L

L

Write Byte c – (DQc and DQPc)

L

H

L

H

H

Write Bytes c, a

L

H

L

H

L

Write Bytes c, b

L

H

L

L

H

Write Bytes c, b, a

L

H

L

L

L

Write Byte d – (DQd and DQPd)

L

L

H

H

H

Write Bytes d, a

L

L

H

H

L

Write Bytes d, b

L

L

H

L

H

Write Bytes d, b, a

L

L

H

L

L

Write Bytes d, c

L

L

L

H

H

Write Bytes d, c, a

L

L

L

H

L

Write Bytes d, c, b

L

L

L

L

H

Write All Bytes

L

L

L

L

L

Function (CY7C1472BV33)

WE

BW

b

BW

a

Read

H

x

x

Write – No Bytes Written

L

H

H

Write Byte a – (DQa and DQPa)

L

H

L

Write Byte b – (DQb and DQPb)

L

L

H

Write Both Bytes

L

L

L

Function (CY7C1474BV33)

WE

BW

x

Read

H

x

Write – No Bytes Written

L

H

Write Byte X − (DQx and DQPx)

L

L

Write All Bytes

L

All

= L

BW

Note

8. Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate Write is based on which Byte Write is active.

Document #: 001-15031 Rev. *C

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Contents Cypress Semiconductor Corporation 198 Champion Court Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1472BV33 4M x Logic Block Diagram CY7C1470BV33 2M xADV/LD Logic Block Diagram CY7C1474BV33 1M xPin Tqfp Pinout Pin ConfigurationsMode CENNC/1G CE2 CLK TDI TDOBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Byte Write Select Inputs, Active LOW. Qualified with Pin Definitions Pin Name IO Type Pin DescriptionFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Address Used Truth TableFunction CY7C1474BV33 Partial Write Cycle DescriptionFunction CY7C1470BV33 BW d BW c BW b BW a Function CY7C1472BV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesGND VIN Vddq TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDV10 Boundary Scan Exit Order 1M xBit # Ball ID E10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description 250 200 167 Unit Min Max Switching CharacteristicsSetup Times A3 A4 Switching WaveformsADV/LD Address DataNOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN/AESA