CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Document History Page
Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-15031
| REV. | ECN No. | Issue Date | Orig. of | Description of Change |
| Change |
| | | | |
| | | | | |
| ** | 1032642 | See ECN | VKN/KKVTMP | New Data Sheet |
| | | | | |
| *A | 1897447 | See ECN | VKN/AESA | Added footnote 15 related to IDD |
| | | | | |
| *B | 2082487 | See ECN | VKN | Converted from preliminary to final |
| | | | | |
| *C | 2159486 | See ECN | VKN/PYRS | Minor Change-Moved to the external web |
| | | | | |
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Document #: 001-15031 Rev. *C | Revised February 29, 2008 | Page 30 of 30 |
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.