Cypress CY7C1474BV33, CY7C1472BV33, CY7C1470BV33 manual NOP, Stall and Deselect Cycles

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Switching Waveforms (continued)

Figure 6 shows NOP, STALL and DESELECT Cycles waveform.[20, 21, 23]

Figure 6. NOP, STALL and DESELECT Cycles

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/LD

WE

BWx

ADDRESS

A1

A2

Data

In-Out (DQ)

WRITE	READ	STALL
D(A1)	Q(A2)

A3	A4			A5
D(A1)	Q(A2)	Q(A3)		D(A4)
READ	WRITE	STALL	NOP	READ
Q(A3)	D(A4)			Q(A5)
	DON’T CARE		UNDEFINED

tCHZ

Q(A5)

DESELECT CONTINUE

DESELECT

Figure 7 shows ZZ Mode timing waveform.[24, 25]

Figure 7. ZZ Mode Timing

CLK

t ZZ

ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes

23.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.

24.Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.

25.IOs are in High-Z when exiting ZZ sleep mode.

Document #: 001-15031 Rev. *C

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Contents Functional Description Selection GuideDescription 250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1470BV33 2M x Logic Block Diagram CY7C1472BV33 4M xLogic Block Diagram CY7C1474BV33 1M x ADV/LDPin Configurations Pin Tqfp PinoutCEN NC/1G CE2 CLKTDI TDO ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Pin Definitions Pin Name IO Type Pin Description Byte Write Select Inputs, Active LOW. Qualified withFunctional Overview ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitTruth Table Operation Address UsedPartial Write Cycle Description Function CY7C1470BV33 BW d BW c BW b BW aFunction CY7C1472BV33 Function CY7C1474BV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing TAP AC Switching Characteristics Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqScan Register Sizes Register Name Bit Size Identification Codes Instruction DescriptionBoundary Scan Exit Order 2M x Bit # Ball ID Boundary Scan Exit Order 4M x Bit # Ball IDBoundary Scan Exit Order 1M x Bit # Ball IDE10 V10Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Setup TimesParameter Description 250 200 167 Unit Min Max Switching Waveforms ADV/LD AddressData A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change VKN/KKVTMPVKN/AESA VKN