Cypress CY7C1474BV33, CY7C1472BV33, CY7C1470BV33 manual ZZ Mode Electrical Characteristics

CY7C1470BV33 CY7C1472BV33, CY7C1474BV33

access (read, write, or deselect) is latched into the Address Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) (or a subset for byte write operations, see “Partial Write Cycle Description” on page 11 for details) inputs is latched into the device and the write is complete.

The data written during the Write operation is controlled by BW (BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472BV33, and BWa,b,c,d,e,f,g,h for CY7C1474BV33) signals. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 provides Byte Write capability that is described in “Partial Write Cycle Description” on page 11. Asserting the Write Enable input (WE) with the selected BW input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte Write capability has been included to greatly simplify read, modify, or write sequences, which can be reduced to simple Byte Write operations.

Because the CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are common IO devices, data must not be driven into the device while the outputs are active. The OE can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) inputs. Doing so tri-states the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 has an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in “Single Write Accesses” on page 8. When ADV/LD is driven HIGH on the subsequent

clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472V33, and BWa,b,c,d,e,f,g,h for CY7C1474BV33) inputs must be driven in each cycle of the burst write to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Table 2. Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address
A1,A0	A1,A0	A1,A0	A1,A0
00	01	10	11
01	00	11	10
10	11	00	01
11	10	01	00
Table 3. Linear Burst Address Table (MODE = GND)
First	Second	Third	Fourth
Address	Address	Address	Address
A1,A0	A1,A0	A1,A0	A1,A0
00	01	10	11
01	10	11	00
10	11	00	01
11	00	01	10

ZZ Mode Electrical Characteristics

Parameter	Description	Test Conditions	Min	Max	Unit
IDDZZ	Sleep mode standby current	ZZ > VDD − 0.2V		120	mA
tZZS	Device operation to ZZ	ZZ > VDD − 0.2V		2tCYC	ns
tZZREC	ZZ recovery time	ZZ < 0.2V	2tCYC		ns
tZZI	ZZ active to sleep current	This parameter is sampled		2tCYC	ns
tRZZI	ZZ Inactive to exit sleep current	This parameter is sampled	0		ns

Document #: 001-15031 Rev. *C Page 9 of 30

[+] Feedback