Cypress CY7C1472BV33, CY7C1474BV33, CY7C1470BV33 manual Ball Fbga 15 x 17 x 1.4 mm

Page 28

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Package Diagrams (continued)

Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

BOTTOM VIEW

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

Ø0.45±0.05(165X)

 

 

11

10

9

8

7

6

5

4

3

2

1

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

B

1.00

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

G

0.25 C

H

J

K

L

M

N

P

R

0.53±0.05

C 0.36

-0.10

+0.05 0.35

SEATING PLANE

1.40 MAX.

0.15 C

17.00±0.10

A

14.00

H

 

 

J

 

K

7.00

L

M

 

 

N

 

P

 

R

 

1.00

 

5.00

 

10.00

B

15.00±0.10

0.15(4X)

 

 

51-85165-*A

Document #: 001-15031 Rev. *C

Page 28 of 30

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Contents Functional Description Selection GuideDescription 250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1470BV33 2M x Logic Block Diagram CY7C1472BV33 4M xLogic Block Diagram CY7C1474BV33 1M x ADV/LDPin Configurations Pin Tqfp PinoutCEN NC/1G CE2 CLKTDI TDO ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Pin Definitions Pin Name IO Type Pin Description Byte Write Select Inputs, Active LOW. Qualified withFunctional Overview ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitTruth Table Operation Address UsedPartial Write Cycle Description Function CY7C1470BV33 BW d BW c BW b BW aFunction CY7C1472BV33 Function CY7C1474BV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing TAP AC Switching Characteristics Parameter Description Min Max Unit ClockOutput Times Hold TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqScan Register Sizes Register Name Bit Size Identification Codes Instruction DescriptionBoundary Scan Exit Order 2M x Bit # Ball ID Boundary Scan Exit Order 4M x Bit # Ball IDBoundary Scan Exit Order 1M x Bit # Ball IDE10 V10Electrical Characteristics Maximum RatingsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms Setup Times Switching CharacteristicsParameter Description 250 200 167 Unit Min Max Switching Waveforms ADV/LD AddressData A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change VKN/KKVTMPVKN/AESA VKN