Cypress CY7C1474BV33, CY7C1472BV33, CY7C1470BV33 manual Boundary Scan Exit Order 2M x Bit # Ball ID

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 9. Boundary Scan Exit Order (2M x 36)

Bit #	165-Ball ID		Bit #		165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	C1		21		R3		41	J11		61	B7

2	D1		22		P2		42	K10		62	B6

3	E1		23		R4		43	J10		63	A6

4	D2		24		P6		44	H11		64	B5

5	E2		25		R6		45	G11		65	A5

6	F1		26		R8		46	F11		66	A4

7	G1		27		P3		47	E11		67	B4

8	F2		28		P4		48	D10		68	B3

9	G2		29		P8		49	D11		69	A3

10	J1		30		P9		50	C11		70	A2

11	K1		31		P10		51	G10		71	B2

12	L1		32		R9		52	F10

13	J2		33		R10		53	E10

14	M1		34		R11		54	A9

15	N1		35		N11		55	B9

16	K2		36		M11		56	A10

17	L2		37		L11		57	B10

18	M2		38		M10		58	A8

19	R1		39		L10		59	B8

20	R2		40		K11		60	A7

Table 10. Boundary Scan Exit Order (4M x 18)

Bit #	165-Ball ID		Bit #		165-Ball ID		Bit #	165-Ball ID		Bit #	165-Ball ID
1	D2		14		R4		27	L10		40	B10

2	E2		15		P6		28	K10		41	A8

3	F2		16		R6		29	J10		42	B8

4	G2		17		R8		30	H11		43	A7

5	J1		18		P3		31	G11		44	B7

6	K1		19		P4		32	F11		45	B6

7	L1		20		P8		33	E11		46	A6

8	M1		21		P9		34	D11		47	B5

9	N1		22		P10		35	C11		48	A4

10	R1		23		R9		36	A11		49	B3

11	R2		24		R10		37	A9		50	A3

12	R3		25		R11		38	B9		51	A2

13	P2		26		M10		39	A10		52	B2

Document #: 001-15031 Rev. *C

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Contents Description 250 MHz 200 MHz 167 MHz Unit Functional DescriptionSelection Guide Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1470BV33 2M x Logic Block Diagram CY7C1472BV33 4M xLogic Block Diagram CY7C1474BV33 1M x ADV/LDPin Configurations Pin Tqfp PinoutTDI TDO CENNC/1G CE2 CLK ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Pin Definitions Pin Name IO Type Pin Description Byte Write Select Inputs, Active LOW. Qualified withFunctional Overview ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitTruth Table Operation Address UsedFunction CY7C1472BV33 Partial Write Cycle DescriptionFunction CY7C1470BV33 BW d BW c BW b BW a Function CY7C1474BV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set TAP Timing Output Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions GND VIN VddqScan Register Sizes Register Name Bit Size Identification Codes Instruction DescriptionBoundary Scan Exit Order 2M x Bit # Ball ID Boundary Scan Exit Order 4M x Bit # Ball IDE10 Boundary Scan Exit Order 1M xBit # Ball ID V10Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Setup TimesParameter Description 250 200 167 Unit Min Max Data Switching WaveformsADV/LD Address A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/AESA ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN