Cypress CY7C1470BV33, CY7C1474BV33, CY7C1472BV33 Switching Waveforms, ADV/LD Address, Data, A3 A4

Page 23

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Switching Waveforms

Figure 5 shows read-write timing waveform.[20, 21, 22]

Figure 5. Read/Write Timing

1

 

2

t CYC

3

 

 

 

 

CLK

 

 

 

 

 

tCENS

tCENH

tCH

tCL

 

CEN

 

 

 

 

 

tCES

tCEH

 

 

 

 

4 5

6

7

8

9

10

 

 

 

 

 

 

 

 

 

 

CE

 

ADV/LD

 

WE

 

BW x

 

ADDRESS

A1

tAS

tAH

Data

 

In-Out (DQ)

 

A2

tDS tDH

D(A1)

A3 A4

tCO

tCLZ

D(A2) D(A2+1)

 

A5

 

A6

A7

 

tDOH

tOEV

tCHZ

 

 

Q(A3)

Q(A4)

 

Q(A4+1)

D(A5)

Q(A6)

 

tOEHZ

 

 

 

 

 

 

 

tDOH

 

 

OE

WRITE

WRITE

BURST

D(A1)

D(A2)

WRITE

 

 

D(A2+1)

 

 

 

 

 

 

 

 

tOELZ

READ

READ

BURST

WRITE

READ

WRITE

DESELECT

Q(A3)

Q(A4)

READ

D(A5)

Q(A6)

D(A7)

 

 

 

Q(A4+1)

 

 

 

 

DON’T CARE

 

UNDEFINED

 

 

 

 

Notes

20.For this waveform ZZ is tied LOW.

21.When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.

22.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.

Document #: 001-15031 Rev. *C

Page 23 of 30

[+] Feedback

Image 23
Contents Cypress Semiconductor Corporation 198 Champion Court Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1472BV33 4M x Logic Block Diagram CY7C1470BV33 2M xADV/LD Logic Block Diagram CY7C1474BV33 1M xPin Tqfp Pinout Pin ConfigurationsMode CENNC/1G CE2 CLK TDI TDOBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Byte Write Select Inputs, Active LOW. Qualified with Pin Definitions Pin Name IO Type Pin DescriptionFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Address Used Truth TableFunction CY7C1474BV33 Partial Write Cycle DescriptionFunction CY7C1470BV33 BW d BW c BW b BW a Function CY7C1472BV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesGND VIN Vddq TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDV10 Boundary Scan Exit Order 1M xBit # Ball ID E10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description 250 200 167 Unit Min Max Switching CharacteristicsSetup Times A3 A4 Switching WaveformsADV/LD Address DataNOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN/AESA