Cypress CY7C1472BV33, CY7C1474BV33 manual Boundary Scan Exit Order 1M x, Bit # Ball ID, E10, V10

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Boundary Scan Exit Order (1M x 72)

Bit #	209-Ball ID		Bit #	209-Ball ID		Bit #	209-Ball ID		Bit #	209-Ball ID
1	A1		29	T1		57	U10		85	B11

2	A2		30	T2		58	T11		86	B10

3	B1		31	U1		59	T10		87	A11

4	B2		32	U2		60	R11		88	A10

5	C1		33	V1		61	R10		89	A7

6	C2		34	V2		62	P11		90	A5

7	D1		35	W1		63	P10		91	A9

8	D2		36	W2		64	N11		92	U8

9	E1		37	T6		65	N10		93	A6

10	E2		38	V3		66	M11		94	D6

11	F1		39	V4		67	M10		95	K6

12	F2		40	U4		68	L11		96	B6

13	G1		41	W5		69	L10		97	K3

14	G2		42	V6		70	P6		98	A8

15	H1		43	W6		71	J11		99	B4

16	H2		44	V5		72	J10		100	B3

17	J1		45	U5		73	H11		101	C3

18	J2		46	U6		74	H10		102	C4

19	L1		47	W7		75	G11		103	C8

20	L2		48	V7		76	G10		104	C9

21	M1		49	U7		77	F11		105	B9

22	M2		50	V8		78	F10		106	B8

23	N1		51	V9		79	E10		107	A4

24	N2		52	W11		80	E11		108	C6

25	P1		53	W10		81	D11		109	B7

26	P2		54	V11		82	D10		110	A3

27	R2		55	V10		83	C11

28	R1		56	U11		84	C10

Document #: 001-15031 Rev. *C

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Contents Cypress Semiconductor Corporation 198 Champion Court Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1472BV33 4M x Logic Block Diagram CY7C1470BV33 2M xADV/LD Logic Block Diagram CY7C1474BV33 1M xPin Tqfp Pinout Pin ConfigurationsMode CENNC/1G CE2 CLK TDI TDOBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Byte Write Select Inputs, Active LOW. Qualified with Pin Definitions Pin Name IO Type Pin DescriptionFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Address Used Truth TableFunction CY7C1474BV33 Partial Write Cycle DescriptionFunction CY7C1470BV33 BW d BW c BW b BW a Function CY7C1472BV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesGND VIN Vddq TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDV10 Boundary Scan Exit Order 1M xBit # Ball ID E10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance CapacitanceAC Test Loads and Waveforms Setup Times Switching CharacteristicsParameter Description 250 200 167 Unit Min Max A3 A4 Switching WaveformsADV/LD Address DataNOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN/AESA