Cypress CY7C1472BV33, CY7C1470BV33 manual Logic Block Diagram CY7C1474BV33 1M x, Adv/Ld

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Logic Block Diagram – CY7C1474BV33 (1M x 72)

 

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

A1

D1

 

Q1

A1'

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A0

D0

BURST

Q0

A0'

 

 

 

 

 

 

 

 

ADV/LD

 

LOGIC

 

 

 

 

 

 

 

CLK

C

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

CEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE ADDRESS

 

WRITE ADDRESS

 

 

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

O

 

 

 

 

 

 

 

 

 

 

 

U

 

U

 

 

 

 

 

 

 

 

 

 

S

T

D

T

 

 

 

 

 

 

 

 

 

 

P

P

 

ADV/LD

 

 

 

 

 

 

 

 

E

U

A

U

 

BW a

 

 

WRITE REGISTRY

 

 

 

 

 

N

T

T

T

 

 

 

 

 

 

 

MEMORY

S

R

A

 

 

BW b

 

 

AND DATA COHERENCY

 

 

 

WRITE

E

S

B

 

 

 

CONTROL LOGIC

 

 

 

ARRAY

A

E

U

 

BW c

 

 

 

 

 

DRIVERS

 

G

T

F

 

BW d

 

 

 

 

 

 

 

 

M

I

E

F

 

 

 

 

 

 

 

 

 

P

S

E

E

 

BW e

 

 

 

 

 

 

 

 

S

T

R

R

 

 

 

 

 

 

 

 

 

E

 

BW f

 

 

 

 

 

 

 

 

 

R

I

S

 

 

 

 

 

 

 

 

 

 

N

 

 

BW g

 

 

 

 

 

 

 

 

 

S

G

 

 

 

 

 

 

 

 

 

 

 

E

E

 

BW h

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

E

 

INPUT

E

 

 

 

 

 

 

 

 

 

REGISTER 1

 

REGISTER 0

 

OE

 

READ LOGIC

 

 

 

 

 

 

 

 

 

 

CE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

 

Sleep

 

 

 

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

 

 

DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph

Document #: 001-15031 Rev. *C

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Contents Cypress Semiconductor Corporation 198 Champion Court Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1472BV33 4M x Logic Block Diagram CY7C1470BV33 2M xADV/LD Logic Block Diagram CY7C1474BV33 1M xPin Tqfp Pinout Pin ConfigurationsMode CENNC/1G CE2 CLK TDI TDOBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Byte Write Select Inputs, Active LOW. Qualified with Pin Definitions Pin Name IO Type Pin DescriptionFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Address Used Truth TableFunction CY7C1474BV33 Partial Write Cycle DescriptionFunction CY7C1470BV33 BW d BW c BW b BW a Function CY7C1472BV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Hold Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Output TimesGND VIN Vddq TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDV10 Boundary Scan Exit Order 1M xBit # Ball ID E10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Setup TimesParameter Description 250 200 167 Unit Min Max A3 A4 Switching WaveformsADV/LD Address DataNOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN ECN No Issue Date Orig. Description of ChangeVKN/KKVTMP VKN/AESA