Cypress CY7C1470BV33, CY7C1474BV33, CY7C1472BV33 manual Ball Fbga 14 x 22 x 1.76 mm

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CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Package Diagrams (continued)

Figure 10. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167

51-85167-**

Document #: 001-15031 Rev. *C

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Contents Selection Guide Functional DescriptionDescription 250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1472BV33 4M x Logic Block Diagram CY7C1470BV33 2M xADV/LD Logic Block Diagram CY7C1474BV33 1M xPin Tqfp Pinout Pin ConfigurationsNC/1G CE2 CLK CENTDI TDO ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Byte Write Select Inputs, Active LOW. Qualified with Pin Definitions Pin Name IO Type Pin DescriptionFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Address Used Truth TableFunction CY7C1470BV33 BW d BW c BW b BW a Partial Write Cycle DescriptionFunction CY7C1472BV33 Function CY7C1474BV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Parameter Description Min Max Unit Clock TAP AC Switching CharacteristicsOutput Times Hold Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions GND VIN VddqIdentification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDBit # Ball ID Boundary Scan Exit Order 1M xE10 V10Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description 250 200 167 Unit Min Max Switching CharacteristicsSetup Times ADV/LD Address Switching WaveformsData A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeVKN/AESA VKN