Cypress CY7C1470BV33, CY7C1474BV33, CY7C1472BV33 manual Scan Register Sizes Register Name Bit Size

Page 17

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Table 6. Identification Register Definitions

Instruction Field

CY7C1470BV33

CY7C1472BV33

CY7C1474BV33

Description

(2M x 36)

(4M x 18)

(1M x 72)

 

 

Revision Number (31:29)

000

000

000

Describes the version number

 

 

 

 

 

Device Depth (28:24)[12]

01011

01011

01011

Reserved for internal use

Architecture/Memory

001000

001000

001000

Defines memory type and archi-

Type(23:18)

 

 

 

tecture

Bus Width/Density(17:12)

100100

010100

110100

Defines width and density

 

 

 

 

 

Cypress JEDEC ID Code

00000110100

00000110100

00000110100

Enables unique identification of

(11:1)

 

 

 

SRAM vendor

ID Register Presence

1

1

1

Indicates the presence of an ID

Indicator (0)

 

 

 

register

Table 7. Scan Register Sizes

Register Name

 

 

Bit Size (x36)

Bit Size (x18)

 

Bit Size (x72)

Instruction

 

3

3

 

3

 

 

 

 

 

 

 

 

Bypass

 

1

1

 

1

 

 

 

 

 

 

 

 

ID

 

32

32

 

32

 

 

 

 

 

 

 

Boundary Scan Order – 165 FBGA

71

52

 

-

 

 

 

 

 

 

 

Boundary Scan Order – 209 FBGA

-

-

 

110

 

 

 

 

 

 

 

Table 8. Identification Codes

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Code

 

 

Description

 

EXTEST

 

000

 

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

IDCODE

 

001

 

Loads the ID register with the vendor ID code and places the register between TDI

 

 

 

 

and TDO. This operation does not affect SRAM operations.

 

SAMPLE Z

 

010

 

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

Forces all SRAM output drivers to a High-Z state.

 

RESERVED

 

011

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

SAMPLE/PRELOAD

 

100

 

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

 

 

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

 

 

 

 

function and is therefore not 1149.1 compliant.

 

RESERVED

 

101

 

Do Not Use: This instruction is reserved for future use.

 

 

 

 

 

 

 

 

 

Note

12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 001-15031 Rev. *C

Page 17 of 30

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Contents Selection Guide Functional DescriptionDescription 250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1472BV33 4M x Logic Block Diagram CY7C1470BV33 2M xADV/LD Logic Block Diagram CY7C1474BV33 1M xPin Tqfp Pinout Pin ConfigurationsNC/1G CE2 CLK CENTDI TDO ModeBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1474BV33 1M × Byte Write Select Inputs, Active LOW. Qualified with Pin Definitions Pin Name IO Type Pin DescriptionFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Address Used Truth TableFunction CY7C1470BV33 BW d BW c BW b BW a Partial Write Cycle DescriptionFunction CY7C1472BV33 Function CY7C1474BV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Instruction Set TAP Timing Parameter Description Min Max Unit Clock TAP AC Switching CharacteristicsOutput Times Hold Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions GND VIN VddqIdentification Codes Instruction Description Scan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 4M x Bit # Ball ID Boundary Scan Exit Order 2M x Bit # Ball IDBit # Ball ID Boundary Scan Exit Order 1M xE10 V10Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description 250 200 167 Unit Min Max Switching CharacteristicsSetup Times ADV/LD Address Switching WaveformsData A3 A4NOP, Stall and Deselect Cycles Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeVKN/AESA VKN