Cypress CY7C1475BV33, CY7C1471BV33, CY7C1473BV33 manual TAP AC Switching Characteristics, TAP Timing

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CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

TAP AC Switching Characteristics

Over the Operating Range[10, 11]

Parameter

Description

Min

Max

Unit

Clock

 

 

 

 

 

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH time

20

 

ns

tTL

TCK Clock LOW time

20

 

ns

Output Times

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

5

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Setup Times

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

TAP Timing

Figure 3. TAP Timing

1

 

2

 

 

 

 

 

 

Test Clock

 

 

 

 

 

 

 

(TCK )

 

 

tTH

 

 

 

 

 

 

 

 

 

 

 

tTM SS

 

tTM SH

 

 

 

 

 

 

 

 

 

Test M ode Select (TM S)

tTDIS tTDIH

Test Data-In (TDI)

Test Data-Out (TDO)

3

4

5

6

tTL

tCY C

 

 

tTDO V

tTDOX

DON’T CA RE

UNDEFINED

Notes

10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 001-15029 Rev. *B

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Contents Description 133 MHz 117 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Single Read Accesses Burst Read AccessesFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address TableLinear Burst Address Table Truth Table Address OperationUsed Truth Table for Read/Write Read/write truth table for CY7C1471BV33 follows.1, 2Function Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set Overview TAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram Circuitry5V TAP AC Test Conditions TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientParameter Description Test Conditions Tqfp Fbga Unit Max CapacitanceThermal Resistance 5V IO Test LoadSwitching Characteristics Parameter Description 133 MHz 117 MHz Unit MinMin Max Rite ReadAddress Switching WaveformsBW AD StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/KKVTMP Issue Orig. of Change Description of Change DateDocument History VKN/AESA