Cypress CY7C1473BV33, CY7C1475BV33, CY7C1471BV33 manual TAP Instruction Set, Overview

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CY7C1471BV33 CY7C1473BV33, CY7C1475BV33

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail in this section.

The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented.

The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which must be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal when in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH).

The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state when performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document #: 001-15029 Rev. *B

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Contents Description 133 MHz 117 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1471BV33 2M x Logic Block Diagram CY7C1473BV33 4M xLogic Block Diagram CY7C1475BV33 1M x Pin Configuration CY7C1471BV33CY7C1473BV33 Ball Fbga 15 x 17 x 1.4 mm Pinout CY7C1471BV33 2M x CY7C1473BV33 4M xBall Fbga 14 x 22 x 1.76 mm Pinout CY7C1475BV33 1M × NC/1GPin Definitions Functional Overview Single Read AccessesBurst Read Accesses Linear Burst Address Table ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table Used Truth TableAddress Operation Function Truth Table for Read/WriteRead/write truth table for CY7C1471BV33 follows.1, 2 Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set OverviewTAP Controller State Diagram TEST-LOGIC Reset RUN-TEST IdleTAP Controller Block Diagram Circuitry5V TAP AC Test Conditions TAP DC Electrical Characteristics and Operating Conditions3V TAP AC Test Conditions GND VIN VddqTAP AC Switching Characteristics TAP TimingIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBit # Ball ID Boundary Scan Exit Order 2M xBoundary Scan Exit Order 4M x Boundary Scan Exit Order 1M x Operating Range Electrical CharacteristicsMaximum Ratings Range AmbientParameter Description Test Conditions Tqfp Fbga Unit Max CapacitanceThermal Resistance 5V IO Test LoadMin Max Switching CharacteristicsParameter Description 133 MHz 117 MHz Unit Min Rite ReadAddress Switching WaveformsBW AD StallZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm VKN/KKVTMP Issue Orig. of Change Description of Change DateDocument History VKN/AESA
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